Commit Graph

1540 Commits

Author SHA1 Message Date
aurel32
75dd595b2e target-ppc: PowerPC 440EP SoC emulation
Wire up the system-on-chip devices present on 440EP chips.

This patch is a little unusual in that qemu doesn't actually emulate the 440
core, but we use this board code with KVM (which does). If/when 440 core
emulation is supported, the kvm_enabled() hack can be removed.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6066 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-16 10:44:06 +00:00
aurel32
b7da58fd27 target-ppc: create a helper function to allow more flexible RAM allocation for PPC 4xx
The 4xx SDRAM controller supports a small number of banks, and each bank must
be one of a small set of sizes. The number of banks and the supported sizes
varies by SoC.

This function uses the user-specified RAM size to fill in the "ram_bases" and
"ram_sizes" arrays required by ppc4xx_sdram_init().

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6063 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 23:15:56 +00:00
aurel32
80e8bd2b0f target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init()
The SDRAM controller is shared across almost all 405 and 440 embedded
processors, with some slight differences such as the sizes supported for each
memory bank.

Rename only; no functional changes.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6062 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 22:59:45 +00:00
aurel32
61b2440503 target-ppc: move PPC4xx SDRAM controller emulation from ppc405_uc.c to ppc4xx_devs.c
The SDRAM controller is shared across almost all 405 and 440 embedded
processors, with some slight differences such as the sizes supported for each
memory bank.

Code movement only; no functional changes.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6061 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 22:59:34 +00:00
blueswir1
09723aa114 Revert part of r5853
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6057 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 20:24:25 +00:00
balrog
997641a84f ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD).
The TSC2102 chip is not included in documentation because a patch is
pending.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 02:05:00 +00:00
balrog
de956597d6 Fix the PXA2xx LCD dirty page detection a little more.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6037 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-15 01:35:39 +00:00
balrog
92fb73b9b0 Fix PXA2xx framebuffer dirty checking.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6019 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 23:57:01 +00:00
blueswir1
1d6198c3b0 Remove unnecessary trailing newlines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-13 09:32:43 +00:00
aurel32
8de2410635 PPC405EP: fix fpga write function
I'm not familiar with this device, but I'm fairly certain the writel handler is
not supposed to recurse.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5995 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:43:07 +00:00
aurel32
c78eae6177 baum: remove 2 warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5994 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 22:42:58 +00:00
aliguori
9b32d5a5f7 pci: virtio: use pci id defines (Gerd Hoffman)
Use the defines added by the previous patch in the virtio drivers.
Also remove the pointless vendor and device args from the
virtio_blk_init() function.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5987 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 21:20:03 +00:00
aliguori
d350d97d19 pci: add default pci subsystem id for all devices (Gerd Hoffman)
This sets a default PCI subsystem ID for all emulated PCI devices.  PCI
specs require this, so do it.

In many cases it is enougth to know the PCI ID to handle a device
correctly.  Sometimes a device driver must identify the exact piece of
hardware (via PCI Subsystem ID) though.

What does this patch to qemu devices:

Right now the emulated PCI devices have no PCI subsystem ID, only the
PCI ID.  The discussed patch sets a default PCI subsystem ID for all
emulated devices.  Which will make the qemu devices look pretty much
like in the laptop case: all PCI subsystem IDs will point to qemu by
default.

If a driver emulates a very specific piece of hardware where it has to
emulate more than just the PCI chip, it can overwrite the PCI subsystem
ID without problems.  The es1370 driver does that for example.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5986 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 21:15:42 +00:00
blueswir1
ad46db9add Rename fls to qemu_fls
Fix compiler warning on OSX, reported by Andreas Faerber.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5982 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 19:37:54 +00:00
blueswir1
85df0de4cf Allow to register a callback with fw_cfg_add_callback()
fw_cfg_add_callback() checks if key has FW_CFG_WRITE_CHANNEL bit set
after masking the key with FW_CFG_ENTRY_MASK.

But as FW_CFG_ENTRY_MASK is ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL),
the bit is never set and function exits.

This patch corrects this by checking the bit before masking the value.

Signed-by-off: Laurent Vivier <Laurent.Vivier@bull.net>
Acked-by: Gleb Natapov <gleb@redhat.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5978 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 17:30:50 +00:00
malc
371bc573e5 Add missing static qualifier
Caught by -Wstrict-prototypes

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5975 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-11 00:14:28 +00:00
aurel32
4fbfcd6d53 IDE: Implement SEEK command
Signed-off-by: Justin Chevrier <theburner1@yahoo.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5972 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 18:17:06 +00:00
aliguori
dd8edf0122 Add 64-bit Block Move support (Direct & Table Indirect) (Ryan Harper)
This patch adds support for 64-bit Block Move instructions.  There are multiple
modes for 64-bit Block moves, direct, indirect, and table indirect.  This patch
implements Direct and Table indirect moves which are needed by 64-bit windows
and SYM_CONF_DMA_ADDRESSING_MODE=2 for the Linux sym53c8xx_2 driver respectively.

Two helper functions are included to check which mode the guest is using.  For
 64-bit direct moves, we fetch a 3rd DWORD and store the value in the DBMS
register.  For Table Indirect moves, we look into the table for which register
contains the upper 32-bits of the 64-bit address.  This selector value indicates
which register to pull the value from and into dnad64 register.

Finally, lsi_do_dma is updated to use the approriate register to build a 64-bit
DMA address if required.

With this patch, Windows XP x64, 2003 SP2 x64, can now install to scsi devices.
Linux SYM_CONF_DMA_ADDRESSING_MODE=2 need a quirk fixup in Patch 4 to function
properly.

Signed-off-by: Ryan Harper <ryanh@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5969 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:38:47 +00:00
aliguori
ab57d96704 LSI53C895A: Rename dmbs register to dbms (Ryan Harper)
Register name should be: Dynamic Block Move Selector (dbms) according to page
 215 of the LSI 53C895A Technical Manual[1].

 1. http://www.lsi.com/DistributionSystem/AssetDocument/files/docs/techdocs/storage_stand_prod/SCSIControllers/lsi53c895a_tech_manual.pdf

Signed-off-by: Ryan Harper <ryanh@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5968 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:37:33 +00:00
aurel32
4efbe58fb5 MIPS Magnum: fix memory-mapped i8042
Current implementation of memory-mapped i8042 controller is atm
implemented with an interface shift (it_shift) parameter, like most all
memory-mapped devices in Qemu.
However, this isn't suitable for MIPS Magnum, where i8042 controller is at
0x80005000 up to 0x80005fff.

Thomas Bogendoerfer (from #mipslinux) tested the behaviour of a real
machine, and found that odd addresses are for status/command register, and
even addresses for data register.

Attached patch implements this behaviour by replacing the it_shift
parameter by a mask one.
Incidentally, keyboard now works on OpenBSD 2.3, which accesses i8042
controller at 0x80005060 and 0x80005061.

Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5962 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10 15:02:07 +00:00
aliguori
f65ed4c152 KVM: Coalesced MMIO support
MMIO exits are more expensive in KVM or Xen than in QEMU because they 
involve, at least, privilege transitions.  However, MMIO write 
operations can be effectively batched if those writes do not have side 
effects.

Good examples of this include VGA pixel operations when in a planar 
mode.  As it turns out, we can get a nice boost in other areas too.  
Laurent mentioned a 9.7% performance boost in iperf with the coalesced 
MMIO changes for the e1000 when he originally posted this work for KVM.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5961 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-09 20:09:57 +00:00
balrog
15b18ec20a Move spitz microdrive to PCMCIA socket 0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5946 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:33:34 +00:00
aurel32
cd5158ea69 MIPS: remove a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5944 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:26:24 +00:00
aurel32
33093a0afc Parallel port reset
Attached patch adds a reset handler to parallel port, so it gets correct
register values after a reset.

(Hervé Poussineau)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5942 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:26:09 +00:00
aurel32
0c34a5d722 target-ppc: kill a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 23:00:00 +00:00
aurel32
d1f193b0ed SH4: SCI improvement
This patch simply implement one register of SH4's SCI := Serial Communication Interface.

R2D evaluation board uses SCI for SPI connection.  So, Linux kernel for R2D with
default configuration causes a QEMU assertion failure when it initializes SPI driver.
This patch avoids it and reduces the kernel config modification work for QEMU.

Completing SCI implementation task is left.  Other board support is desirable to confirm
this task, which uses SCI for a serial terminal.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5939 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 22:46:49 +00:00
aurel32
b79e175259 SH4: kill a few warnings
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 22:46:42 +00:00
balrog
5c16736a37 SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).
Main purpose of this is to delete
       *physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.

Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.

Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:39:58 +00:00
balrog
486579de70 SH: improve the way sh7750 registers io memory (Takashi YOSHII).
Fixes to be needed for commit #5849 "Change MMIO callbacks..."
 hw/sh7750.c:
  - Divide region of CPU control registers to avoid overlapping
    to peripheral modules.
  - Delete unused var "icr", which had moved to hw/sh_intc.c.
 hw/sm501.c:
  - Merge non page aligned palette registers into the region of
    control registers.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:33:15 +00:00
blueswir1
69d6451c3e Fix some new warnings introduced after r5022
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5933 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:30:18 +00:00
balrog
c2f01775dd SH: r2d pci support (Takashi YOSHII).
This patch adds pci support to sh/r2d board.
This is the first user of PCIC support I formerly sent.

PCIC actually is inside of chip with CPU core on SH7751.
But, this code is written as if SH7750 and PCIC are on board.
I care little about physical device boundary, but fitting with qemu's
design.

This patch also adds some BSC (Bus State Controller) registers,
because PCI device driver software have to accesses them.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:20:43 +00:00
balrog
d0ef528a3e SH: Don't subtract bases from access addresses in PCIC.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5928 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:13:12 +00:00
balrog
1e5459a3fa SH: On-chip PCI controller support (Takashi YOSHII).
This patch adds SuperH on-chip PCI controller(PCIC) support.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 19:08:45 +00:00
balrog
d47ede6093 sh4: Add r2d onboard FPGA IRQ controller (Takashi YOSHII).
This adds IRQ controller in FPGA on r2d, and use it for CF.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5926 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:59:57 +00:00
balrog
c6d86a33d3 sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).
This patch adds IRL(4bit encoded 15 level interrupt input) support
to SH using qemu_irq as a multi level (!=on/off) signal.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:49:57 +00:00
balrog
a4a771c055 sh4: mmio based CF support on r2d board (Takashi YOSHII).
This patch adds emulation for a CompactFlash on sh4/r2d board.
 The device is CF, but wired to be worked as True-IDE mode, and connected
 directly to SH bus. So, this code is to support generally mmio based
 IDEs which are supported by "pata_platform" driver in linux kernel.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5924 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:41:42 +00:00
balrog
dc23e2605d PXA: Account for offset from page start in a subpage mapping.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5917 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 16:08:49 +00:00
balrog
1364332320 omap1: fix uart3 init (Jean-Christophe PLAGNIOL-VILLARD).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5906 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 12:52:07 +00:00
balrog
c588de3d27 omap1: add OSC_12M_SEL UART register support (original patch from Jean-Christophe PLAGNIOL-VILLARD)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5905 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 12:49:26 +00:00
balrog
d361be2566 pflash_cfi01: add Single Byte Program (Jean-Christophe PLAGNIOL-VILLARD).
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5904 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 12:36:28 +00:00
balrog
575750581c SCSI: Handle inquiry commands of varying length (Justin Chevrier).
Openserver 5.0.5 sends an Inquiry command to the emulated SCSI disk
expecting a response length of 40 bytes. Currently the response to an
Inquiry command is hardcoded to 36 bytes. When receiving a response of
length 36 instead of 40 Openserver panics.

Modifications to original patch based on feedback from Ryan Harper and Paul
Brook. Thanks guys.

Signed-off-by: Justin Chevrier <address@hidden>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5903 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 03:12:54 +00:00
balrog
02b373ad5d LSI53C895A: Handle empty SCRIPTS opcode (Justin Chevrier)
Basically after each DMA transfer the Openserver driver would issue an
empty (0) SCRIPTS opcode. As the opcode is essentially a NOP it has no
second DWORD and therefore the DSP should only be incremented by 4 bytes
instead of the 8 bytes we currently do.

Here's a snippet of the log:

lsi_scsi: Data ready tag=0x100d9 len=16384
...
lsi_scsi: SCRIPTS dsp=068c5e50 opcode 01000400 arg 07a09000
lsi_scsi: DMA addr=0x07a09000 len=1024
lsi_scsi: SCRIPTS dsp=068c5e58 opcode 00000000 arg 01000400
lsi_scsi: Wrong phase got 1 expected 0

Note the 2nd DWORD after the empty opcode; the next opcode in the DMA
transfer sequence. As can be expected the address after that has the next
DMA address to use.

After the attached patch the DMA transfer is able to complete successfully:

lsi_scsi: SCRIPTS dsp=068c5e50 opcode 01000400 arg 07a0d000
lsi_scsi: DMA addr=0x07a0d000 len=1024
lsi_scsi: SCRIPTS dsp=068c5e5c opcode 01000400 arg 07a0d400
lsi_scsi: DMA addr=0x07a0d400 len=1024
...

Tested againsted Openserver 5.0.5 and Debian ARM.

Signed-off-by: Justin Chevrier <address@hidden>
Acked-by: Ryan Harper <ryanh@us.ibm.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 03:07:51 +00:00
balrog
c021db86a4 LSI53C895A: Remove current_dma_len hack
Signed-off-by: Justin Chevrier <address@hidden>
Acked-by: Ryan Harper <ryanh@us.ibm.com>
Acked-by: Chris Wright <chrisw@sous-sol.org>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5901 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 03:03:21 +00:00
balrog
9e7d11ff34 Remove a duplicate omap_l4_attach(), add one missing elsewhere.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5900 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 01:51:28 +00:00
balrog
ed00525318 Don't wrap I2C registers addresses on PXA270.
This way the registers will only be visible at the given offset instead of
every 0x100 bytes.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5899 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 01:49:28 +00:00
edgar_igl
e63204853e ETRAX-FS: Simplify the DMA blocks address registration and decoding.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5898 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 00:14:21 +00:00
edgar_igl
0db74b0705 ETRAX-FS: No need to decode the address anymore.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5897 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 23:19:03 +00:00
aurel32
3b63c04e1b Revert "hw/apic.c: use fls() from host-utils"
This reverts commit 5876.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5890 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-06 10:46:35 +00:00
aliguori
bf9298b90e Make struct iovec universally available
Vectored IO APIs will require some sort of vector argument.  It makes sense to
use struct iovec and just define it globally for Windows.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5889 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-05 20:05:26 +00:00
blueswir1
a38131b669 Attached patch contains warning fixes.
Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5888 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-05 17:56:40 +00:00