Commit Graph

451 Commits

Author SHA1 Message Date
Aleksandar Markovic
ca693d1c92 tests/tcg: target/mips: Add utility function reset_msa_registers()
Add function reset_msa_registers() and utilize it in each MSA test.
This is needed to ensure independency of test results on the state of
MSA registers before test execution. This also allows for correction
of tests for VSHF* instructions, that are now independent on the
previous state of MSA registers.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
b7c6798220 tests/tcg: target/mips: Move four tests to a better location
Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory
to "fixed-point multiply" directory, since they do not operate on
integers, but on fixed point numbers.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
99d423e576 tests/tcg: target/mips: Add tests for MSA shift instructions
Add tests for MSA shift instructions. This includes following
instructions:

  * SLL.B - shift left logical (bytes)
  * SLL.H - shift left logical (halfwords)
  * SLL.W - shift left logical (words)
  * SLL.D - shift left logical (doublewords)
  * SRA.B - shift right arithmetic (bytes)
  * SRA.H - shift right arithmetic (halfwords)
  * SRA.W - shift right arithmetic (words)
  * SRA.D - shift right arithmetic (doublewords)
  * SRAR.B - shift right arithmetic rounded (bytes)
  * SRAR.H - shift right arithmetic rounded (halfwords)
  * SRAR.W - shift right arithmetic rounded (words)
  * SRAR.D - shift right arithmetic rounded (doublewords)
  * SRL.B - shift right logical (bytes)
  * SRL.H - shift right logical (halfwords)
  * SRL.W - shift right logical (words)
  * SRL.D - shift right logical (doublewords)
  * SRLR.B - shift right logical rounded (bytes)
  * SRLR.H - shift right logical rounded (halfwords)
  * SRLR.W - shift right logical rounded (words)
  * SRLR.D - shift right logical rounded (doublewords)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
6ec12d4feb tests/tcg: target/mips: Amend and rearrange MSA wrappers
Amend and rearrange MSA wrappers to follow the same organization as
in MSA tests.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
1d336c87a3 tests/tcg: target/mips: Add tests for MSA bit set instructions
Add tests for MSA bit set instructions. This includes following
instructions:

  * BCLR.B - clear bit (bytes)
  * BCLR.H - clear bit (halfwords)
  * BCLR.W - clear bit (words)
  * BCLR.D - clear bit (doublewords)
  * BNEG.B - negate bit (bytes)
  * BNEG.H - negate bit (halfwords)
  * BNEG.W - negate bit (words)
  * BNEG.D - negate bit (doublewords)
  * BSET.B - set bit (bytes)
  * BSET.H - set bit (halfwords)
  * BSET.W - set bit (words)
  * BSET.D - set bit (doublewords)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1555699081-24577-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01 20:20:20 +02:00
Aleksandar Markovic
750541c492 target/mips: Amend and cleanup MSA TCG tests
Add missing bits and peaces of the tests of the emulation of certain
MSA (non-immediate variants): some tests were missing two last cases;
some instructions were missing wrappers; some test included wrong
headers; some tests were missing altogether; updated some copywright
preambles; do several other minor cleanups.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1555699081-24577-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01 20:20:20 +02:00
David Gibson
c10aaaab0f tests: Fix up docker cross builds for ppc64 (BE) targets
We currently have docker cross building targets for powerpc (32-bit, BE)
and ppc64el (64-bit, LE), but not for pcp64 (64-bit, BE).  This is an
irritating gap in make check-tcg coverage so correct it.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29 11:14:19 +10:00
Richard Henderson
8d8a8ab544 tests/tcg/alpha: add system boot.S
This provides the bootstrap and low level helper functions for an
alpha kernel.  We use direct access to the DP264 serial port for
test output, and hard machine halt to exit the emulation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20190501184306.15208-1-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
7ac283e963 tests/tcg/multiarch: expand system memory test to cover more
Expand the memory test to cover move of the softmmu code. Specifically
we:

  - improve commentary
  - add some helpers (for later BE support)
  - reduce boiler plate into helpers
  - add signed reads at various sizes/offsets
  - required -DCHECK_UNALIGNED

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
936647d3fc tests/tcg/minilib: support %c format char
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
67f3da9d74 tests/tcg/multiarch: move the system memory test
There is nothing inherently architecture specific about the memory
test although we may have to manage different restrictions of
unaligned access across architectures.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
f6482872f3 tests/tcg/aarch64: add system boot.S
This provides the bootstrap and low level helper functions for an
aarch64 kernel. We use semihosting to handle test output and exiting
the emulation. semihosting's parameter passing is a little funky so we
end up using the stack and pointing to that as the parameter block.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
49d755d02e tests/tcg/multiarch: add hello world system test
This is not really i386 only, we can have the same test for all
architectures supporting system tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
8041650aef tests/tcg/multiarch: add support for multiarch system tests
We can certainly support some common tests for system emulation that
make use of our minimal defined boot.S support. It will still be up to
individual architectures to ensure they build so we provide a
MULTIARCH_TESTS variable that they can tack onto TESTS themselves.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Max Filippov
b345e14053 target/xtensa: implement exclusive access option
The Exclusive Instructions provide a general-purpose mechanism for
atomic updates of memory-based synchronization variables that can be
used for exclusion algorithms.

Use cmpxchg-based implementation that is sufficient for the typical use
of exclusive access in atomic operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-15 10:31:52 -07:00
Max Filippov
bc19449acc tests/tcg/xtensa: clean up test set
Drop test_fail: we know that exit simcall works. Now that it's not run
automatically there's no point in keeping it.
Drop test_pipeline: we're not modeling pipeline, we don't control ccount
and there's no plan to do so.
Enable test_boolean: it won't break on cores without boolean option, it
will do testing on cores with boolean option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-23 14:42:05 -07:00
Max Filippov
b9ec52188f target/xtensa: fix break_dependency for repeated resources
break_dependency incorrectly handles the case of dependency on an opcode
that references the same register multiple times. E.g. the following
instruction is translated incorrectly:

  { or a2, a3, a3 ; or a3, a2, a2 }

This happens because resource indices of both dependency graph nodes are
incremented, and a copy for the second instance of the same register in
the ending node is not done.
Only increment resource index of the ending node of the dependency.
Add test.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-21 21:47:50 -07:00
Alex Bennée
b640728151 tests/tcg/arm: account for pauth randomness
Pointer authentication isn't guaranteed to always detect a clash
between different keys. Take this into account in the test by running
several times and checking the percentage hit rate of the test.

Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
8a2af7a70c tests/tcg/i386: add memory test to exercise softmmu
This is a simple test to check various access patterns to memory
including unaligned access.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
40d6ee9450 tests/tcg/i386: add system mode Hello World test
This introduces the build framework for simple i386 system tests. The
first test is the eponymous "Hello World" which simply outputs the
text on the serial port and then exits.

I've included the framework for x86_64 but it is not in this series as
it is a work in progress.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
a113ec989b tests/tcg: provide a minilib for system tests
We will likely want a few common functions to make up for the fact we
don't have a libc and we don't want to feel like we are programming by
banging rocks together.

I've purloined the printf function from:

  https://git.virtualopensystems.com/dev/tcg_baremetal_tests

Although I have tweaked the names to avoid confusing GCC about clashing
with builtins.

Cc: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
Cc: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d72132c02e tests/tcg: enable cris base user-mode tests
This converts the existing Makefile into a Makefile.target and updates
it so it can be called by the tcg build system. The original Makefile
didn't set -cpu except for the v17 tests however that has broken (I
assume because linux-user is a "max" cpu) so here I force it to be
crisv17.

I've also replicated the GNU simulator targets (run-FOO-on-sim).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
f17365f518 tests/tcg/cris: align mul operations
To avoid:

  Error: dangerous MULS/MULU location; give it higher alignment

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
0056cb5790 tests/tcg/cris: comment out the ccs test
Evidently upstream gcc doesn't like this opcode.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d4f6e58fcb tests/tcg: split cris tests into bare and libc directories
Bare tests are standalone assembly tests that don't require linking to
any libc and hence can be built with kernel only compilers. The libc
tests need a compiler capable of building properly linked userspace
binaries. As we don't have such a cross compiler at the moment we
won't be building those tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
6b970dd62c tests/tcg/cris: cleanup sys.c
This is a mini library which provides helper functions to the tests
which are all currently written in assembly. A bunch of minor changes:

      - removed libc related headers (fedora-cris-cross is a system compiler)
      - re-organised the functions to avoid forward declarations
      - cleaned up brace usage
      - restored exit for _fail case
      - removed tabs and fixed indentation

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Stefan Hajnoczi
647aee9ba2 tests/tcg/arm: add ARMv6-M UNDEFINED 32-bit instruction test
Test that 32-bit instructions declared UNDEFINED in the ARMv6-M
Reference Manual really do raise an exception.  Also test that the 6
32-bit instructions defined in the ARMv6-M Reference Manual do not raise
an exception.

Based-on: <20181029194519.15628-1-stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20181129185113.30353-1-stefanha@redhat.com>
[AJB: integrated into system tests]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
be5cac175a tests/tcg/xtensa: enable system tests
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Philippe Mathieu-Daudé
c72d9df181 tests/docker: add debian-xtensa-cross image
Xtensa cpu supported:
- dc232b
- dc233c
- csp

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
b4f396151b tests/tcg/mips: fix hello-mips compilation
The compilation flags for proper building are in the source tree. We
also fix exit to 0 so the result is counted as a success.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d0ce6257c6 tests/tcg: add gdb runner variant
With this you can launch a test in gdb with:

  cd $(BUILD)/tests
  make -f $(SRC)/tests/tcg/Makefile gdb-$(TEST_NAME)

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
fdfda70e28 tests/tcg: split run-test into user and system variants
We can't rely on shell redirect magic to get things right so lets
setup a common output chardev that is expecting to write to files. As
we have split run-test up we might as well move the default monitor
bits into the call.

Finally a little make sophistry is required to correctly quote
$(COMMA) and as we don't inherit common rules we have our own little
copy here.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
3d55c02624 tests/tcg: add QEMU_OPT option for test runner
This will allow tests to modify the QEMU invocation with for example
different -cpu stazas without having to define a whole new set of
runner types.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
bd15e6e004 tests/tcg: add softmmu awareness to Makefile
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12 17:05:21 +00:00
Mateja Marjanovic
53e116fed6 target/mips: Add tests for a variety of MSA integer subtract instructions
Add tests for a variety of MSA integer subtract instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-6-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
4b302ce90d target/mips: Add tests for a variety of MSA integer multiply instructions
Add tests for a variety of MSA integer multiply instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-5-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
a8f91dd9fd target/mips: Add tests for a variety of MSA integer dot product instructions
Add tests for a variety of MSA integer dot product instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
72f463bc08 target/mips: Add tests for a variety of MSA integer divide instructions
Add tests for a variety of MSA integer divide instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
1be82d8901 target/mips: Add tests for a variety of MSA integer average instructions
Add tests for a variety of MSA integer average instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Aleksandar Markovic
81526dff27 tests/tcg: target/mips: Rename two header files for consistency
Rename two header files for consistency and clarity. Do all other
changes to accommodate new names.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <amarkovic@wavecomp.com>
Message-Id: <1551981716-30664-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-11 12:36:58 +01:00
Aleksandar Markovic
dd8d6a2d5a tests/tcg: target/mips: Correct preambles of test source files
Correct preambles of test source files.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <amarkovic@wavecomp.com>
Message-Id: <1551981716-30664-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-11 12:36:49 +01:00
Mateja Marjanovic
0fdd986a6c target/mips: Add tests for integer add MSA instruction group
These are the regression tests for integer addition MSA instruction
- various flavors of instruction add (ADD, ADDS, HADD,...).

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551718283-4487-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-05 17:05:33 +01:00
Aleksandar Markovic
2a367db039 tests/tcg: target/mips: Add tests for MSA pack instructions
Add tests for MSA pack instructions. This includes following
instructions:

  * PCKEV.B - pack even (bytes)
  * PCKEV.H - pack even (halfwords)
  * PCKEV.W - pack even (words)
  * PCKEV.D - pack even (doublewords)
  * PCKOD.B - pack odd (bytes)
  * PCKOD.H - pack odd (halfwords)
  * PCKOD.W - pack odd (words)
  * PCKOD.D - pack odd (doublewords)
  * VSHF.B - data preserving shuffle (bytes)
  * VSHF.H - data preserving shuffle (halfwords)
  * VSHF.W - data preserving shuffle (words)
  * VSHF.D - data preserving shuffle (doublewords)

Each test consists of 80 test cases, so altogether there are 960
test cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:44 +01:00
Aleksandar Markovic
7ecdacc568 tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructions
Add tests for MIPS64R6 integer multiply instructions: MUL, MUH, MULU,
MUHU, DMUL, DMUH, DMULU, and DMUHU.

MUH and MUHU require 64 bit inputs in the form of 64-bit sign-extended
32-bit inputs.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-14-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:33 +01:00
Aleksandar Markovic
09a1bc758e tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions
Add tests for MIPS64R6 shift instructions: SLLV, SRLV, SRAV, DSLLV,
DSRLV, and DSRAV.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:24 +01:00
Aleksandar Markovic
9dea2df848 tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions
Add tests for MIPS64R6 bit count instructions: CLO, CLZ, DCLO, and DCLZ.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-12-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:15 +01:00
Aleksandar Markovic
8708c32a47 tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions
Add tests for MIPS64R6 bit swap instructions: BITSWAP and DBITSWAP.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:04 +01:00
Aleksandar Markovic
99d46107f7 tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions
Add tests for MIPS64R6 logic instructions: AND, NOR, OR, and XOR.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:54 +01:00
Aleksandar Markovic
50dccc057f tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions
Add wrappers for some MIPS64R6 instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:46 +01:00
Aleksandar Markovic
6ae2e3bb33 tests/tcg: target/mips: Extend functionality of MSA wrapper macros
Add macros that will allow testing cases when one of the source
registers is identical to the destination register.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:37 +01:00
Aleksandar Markovic
dd3ba7036f tests/tcg: target/mips: Fix test utilities for 128-bit tests
Add "static" and "const" modifiers where appropriate, and fix other
minor issues.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:30 +01:00
Aleksandar Markovic
ace4458466 tests/tcg: target/mips: Add test utilities for 64-bit tests
Add test utilities for 64-bit tests. Some of MIPS64R6 instructions
require 64-bit inputs to be 32-bit integers sign-extedned to 64 bits,
hence the need for sets of such inputs.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:22 +01:00
Aleksandar Markovic
26b3256392 tests/tcg: target/mips: Add test utilities for 32-bit tests
Add test utilities for 32-bit tests.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:13 +01:00
Aleksandar Markovic
9e9509421f tests/tcg: target/mips: Add wrappers for various MSA instructions
Add wrappers for various MSA integer instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:03 +01:00
Peter Maydell
4179575898 target/xtensa: FLIX support, various fixes and test improvements
- add FLIX (flexible length instructions extension) support;
 - make testsuite runnable on wider range of xtensa cores;
 - add floating point opcode tests;
 - don't add duplicate 'static' in import_core.sh script;
 - fix undefined opcodes detection in test_mmuhifi_c3 overlay.
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Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.

# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190228-xtensa: (40 commits)
  tests/tcg/xtensa: add FPU2000 coprocessor tests
  tests/tcg/xtensa: add FP1 group tests
  tests/tcg/xtensa: add FP0 group conversion tests
  tests/tcg/xtensa: add FP0 group arithmetic tests
  tests/tcg/xtensa: add LSCI/LSCX group tests
  tests/tcg/xtensa: add test for FLIX
  tests/tcg/xtensa: conditionalize MMU-related tests
  tests/tcg/xtensa: conditionalize windowed register tests
  tests/tcg/xtensa: conditionalize and fix s32c1i tests
  tests/tcg/xtensa: fix SR tests for big endian configs
  tests/tcg/xtensa: conditionalize and expand SR tests
  tests/tcg/xtensa: conditionalize timer/CCOUNT tests
  tests/tcg/xtensa: conditionalize interrupt tests
  tests/tcg/xtensa: add straightforward conditionals
  tests/tcg/xtensa: conditionalize cache option tests
  tests/tcg/xtensa: conditionalize debug option tests
  tests/tcg/xtensa: enable boolean tests
  tests/tcg/xtensa: fix endianness issues in test_b
  tests/tcg/xtensa: don't use optional opcodes in generic code
  tests/tcg/xtensa: support configs with LITBASE
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28 19:04:16 +00:00
Max Filippov
de0cebd930 tests/tcg/xtensa: add FPU2000 coprocessor tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:24 -08:00
Max Filippov
fd78bc55a4 tests/tcg/xtensa: add FP1 group tests
Test comparisons and conditional move operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:24 -08:00
Max Filippov
710b15f041 tests/tcg/xtensa: add FP0 group conversion tests
Test conversions for normal, NaN and Inf arguments.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9d012e8ec2 tests/tcg/xtensa: add FP0 group arithmetic tests
Test arithmetic operations for normal, NaN and Inf arguments.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
5e33b037b5 tests/tcg/xtensa: add LSCI/LSCX group tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
ebbd775aab tests/tcg/xtensa: add test for FLIX
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
3db8a95e70 tests/tcg/xtensa: conditionalize MMU-related tests
Make MMU-related tests conditional on the presence of MMUv2 option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
c20e10eac8 tests/tcg/xtensa: conditionalize windowed register tests
Make windowed register tests conditional on the presence of this option.
Fix tests to work correctly for both 32 and 64 physical registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
00988da486 tests/tcg/xtensa: conditionalize and fix s32c1i tests
Make s32c1i tests conditional on the presence of this option. Initialize
ATOMCTL SR when it's present to allow RCW transactions on uncached
memory.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9b2d08a066 tests/tcg/xtensa: fix SR tests for big endian configs
SR tests generate instructions that the assembler does not recognize and
thus must take care about configuration endianness.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
50d3a0feae tests/tcg/xtensa: conditionalize and expand SR tests
Make tests for specific special registers conditional on the presence of
the options that add these registers and test that the registers are not
accessible otherwise.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
02a5a4a877 tests/tcg/xtensa: conditionalize timer/CCOUNT tests
Make timer/CCOUNT tests conditional on the presence of timer option and
number of configured timers. Don't use hard coded interrupt levels for
timers, use configured values.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9c98822619 tests/tcg/xtensa: conditionalize interrupt tests
Make interrupt tests conditional on the presence of interrupt option and
on the presence of level-1 and high level software interrupts. Don't use
hard-coded interrupt level for the high level interrupt tests, choose
high level software IRQ and use its configured level.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
50f0171a95 tests/tcg/xtensa: add straightforward conditionals
Make tests for optional instruction groups conditional on the presence
of corresponding options in the config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
ecf5b57759 tests/tcg/xtensa: conditionalize cache option tests
Make data/instruction tests conditional on the presence of
data/instruction cache, whether they're lockable and whether data cache
is writeback.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
66c58ba71b tests/tcg/xtensa: conditionalize debug option tests
Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data breakpoint registers on the corresponding definitions. Use
configured debug interrupt level instead of the hardcoded value to set
up IRQ handler and access debug EPC register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
912f161ff7 tests/tcg/xtensa: enable boolean tests
Uncomment test_boolean in the test makefile. Make actual tests code
conditional on the presence of boolean option in the config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
64eef9bf95 tests/tcg/xtensa: fix endianness issues in test_b
Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that
accept little-endian bit number and produce correct immediate for both
little and big endian configurations. Choose value loaded into register
for bbc/bbs opcodes based on configuration endianness.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
fafd553343 tests/tcg/xtensa: don't use optional opcodes in generic code
Don't use 'loop' opcode in generic testsuite completion code, only use
core opcodes to make it work with any configuration.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
306a69dad4 tests/tcg/xtensa: support configs with LITBASE
Configurations with LITBASE register may use absolute literals by
default. Pass --no-absolute-literals option to assembler to use
PC-relative literals instead.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
906da88291 tests/tcg/xtensa: support configurations w/o vecbase
Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sections by assigning next offset to dot, as it may sometimes move dot
backwards and sometimes they may even belong to different memory region.
Don't group vectors into single output section. Instead put each vector
into its own section ant put it at its default virtual address.
Reserve 4KBytes from the default vectors base and put rest of the code
and data starting from there. Mark vectors sections as executable,
otherwise their contents is discarded. There may be as little as 16
bytes reserved for some vectors, load handler address into a0 and use
ret.n to jump there to make vector code fit into this 16 byte space.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
0ed040db36 tests/tcg/xtensa: indicate failed tests
When test suite with multiple tests fails it's not obvious which test
failed. Pring "failed" in every invocation of test_fail. Do printing
when DEBUG preprocessor macro is defined.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Aleksandar Markovic
1e6bea794c tests/tcg: target/mips: Add tests for MSA integer max/min instructions
Add tests for MSA integer max/min instructions. This includes
following instructions:

  * MAX_A.B - maximum of absolute of two signed values (bytes)
  * MAX_A.H - maximum of absolute of two signed values (halfwords)
  * MAX_A.W - maximum of absolute of two signed values (words)
  * MAX_A.D - maximum of absolute of two signed values (doublewords)
  * MIN_A.B - minimum of absolute of two signed values (bytes)
  * MIN_A.H - minimum of absolute of two signed values (halfwords)
  * MIN_A.W - minimum of absolute of two signed values (words)
  * MIN_A.D - minimum of absolute of two signed values (doublewords)
  * MAX_S.B - maximum of two signed values (bytes)
  * MAX_S.H - maximum of two signed values (halfwords)
  * MAX_S.W - maximum of two signed values (words)
  * MAX_S.D - maximum of two signed values (doublewords)
  * MIN_S.B - minimum of two signed values (bytes)
  * MIN_S.H - minimum of two signed values (halfwords)
  * MIN_S.W - minimum of two signed values (words)
  * MIN_S.D - minimum of two signed values (doublewords)
  * MAX_U.B - maximum of two unsigned values (bytes)
  * MAX_U.H - maximum of two unsigned values (halfwords)
  * MAX_U.W - maximum of two unsigned values (words)
  * MAX_U.D - maximum of two unsigned values (doublewords)
  * MIN_U.B - minimum of two unsigned values (bytes)
  * MIN_U.H - minimum of two unsigned values (halfwords)
  * MIN_U.W - minimum of two unsigned values (words)
  * MIN_U.D - minimum of two unsigned values (doublewords)

Each test consists of 80 test cases, so altogether there are 1920
test cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
1f3a111ecc tests/tcg: target/mips: Add wrappers for MSA integer max/min instructions
Add wrappers for MSA integer max/min instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
520e210c0a tests/tcg: target/mips: Add tests for MSA integer compare instructions
Add tests for MSA integer compare instructions. This includes
following instructions:

  * CEQ.B - integer compare equal (bytes)
  * CEQ.H - integer compare equal (halfwords)
  * CEQ.W - integer compare equal (words)
  * CEQ.D - integer compare equal (doublewords)
  * CLE_S.B - signed integer compare less or equal (bytes)
  * CLE_S.H - signed integer compare less or equal (halfwords)
  * CLE_S.W - signed integer compare less or equal (words)
  * CLE_S.D - signed integer compare less or equal (doublewords)
  * CLE_U.B - unsigned integer compare less or equal (bytes)
  * CLE_U.H - unsigned integer compare less or equal (halfwords)
  * CLE_U.W - unsigned integer compare less or equal (words)
  * CLE_U.D - unsigned integer compare less or equal (doublewords)
  * CLT_S.B - signed integer compare less or equal (bytes)
  * CLT_S.H - signed integer compare less or equal (halfwords)
  * CLT_S.W - signed integer compare less or equal (words)
  * CLT_S.D - signed integer compare less or equal (doublewords)
  * CLT_U.B - unsigned integer compare less or equal (bytes)
  * CLT_U.H - unsigned integer compare less or equal (halfwords)
  * CLT_U.W - unsigned integer compare less or equal (words)
  * CLT_U.D - unsigned integer compare less or equal (doublewords)

Each test consists of 80 test cases, so altogether there are 1600 test
cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
a4719aa85e tests/tcg: target/mips: Add wrappers for MSA integer compare instructions
Add wrappers for MSA integer compare instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
e7bbc9b1c2 tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count'
Change directory name 'bit-counting' to 'bit-count'. This is just for
cosmetic and consistency sake. This was the only subdirectory in MSA
test directory that uses ending 'ing'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
1f69d17856 tests/tcg: target/mips: Correct path to headers in some test source files
Correct path to headers in tests/tcg/mips/user/ase/msa/bit-counting/*
source files.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
ba63292445 tests/tcg: target/mips: Add tests for MSA logic instructions
Add tests for MSA logic instructions. This includes following
instructions:

  * AND.V - logical AND
  * NOR.V - logical NOR
  * OR.V - logical OR
  * XOR.V - logical XOR

Each test consists of 80 test cases, so altogether there are 320
test cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
db37850bb4 tests/tcg: target/mips: Add wrappers for MSA logic instructions
Add wrappers for MSA logic instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
fc76f48667 tests/tcg: target/mips: Add tests for MSA interleave instructions
Add tests for MSA interleave instructions. This includes following
instructions:

  * ILVEV.B - interleave even (bytes)
  * ILVEV.H - interleave even (halfwords)
  * ILVEV.W - interleave even (words)
  * ILVEV.D - interleave even (doublewords)
  * ILVOD.B - interleave odd (bytes)
  * ILVOD.H - interleave odd (halfwords)
  * ILVOD.W - interleave odd (words)
  * ILVOD.D - interleave odd (doublewords)
  * ILVL.B - interleave left (bytes)
  * ILVL.H - interleave left (halfwords)
  * ILVL.W - interleave left (words)
  * ILVL.D - interleave left (doublewords)
  * ILVR.B - interleave right (bytes)
  * ILVR.H - interleave right (halfwords)
  * ILVR.W - interleave right (words)
  * ILVR.D - interleave right (doublewords)

Each test consists of 80 test cases, so altogether there are 1280
test cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
afdc3c515a tests/tcg: target/mips: Add wrappers for MSA interleave instructions
Add wrappers for MSA interleave instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
b62592ab65 tests/tcg: target/mips: Add tests for MSA bit counting instructions
Add tests for MSA bit counting instructions. This includes following
instructions:

  * NLOC.B - number of leading ones (bytes)
  * NLOC.H - number of leading ones (halfwords)
  * NLOC.W - number of leading ones (words)
  * NLOC.D - number of leading ones (doublewords)
  * NLZC.B - number of leading zeros (bytes)
  * NLZC.H - number of leading zeros (halfwords)
  * NLZC.W - number of leading zeros (words)
  * NLZC.D - number of leading zeros (doublewords)
  * PCNT.B - population count / number of ones (bytes)
  * PCNT.H - population count / number of ones (halfwords)
  * PCNT.W - population count / number of ones (words)
  * PCNT.D - population count / number of ones (doublewords)

Each test consists of 80 test cases, so altogether there are 960 test
cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
85c2a39300 tests/tcg: target/mips: Add wrappers for MSA bit counting instructions
Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
08857c882d tests/tcg: target/mips: Add a header with test utilities
Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
d33f672861 tests/tcg: target/mips: Add a header with test inputs
The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
51a0e80c6e tests/tcg: target/mips: Remove an unnecessary file
Remove a file that was added long time ago by mistake. The commit
that introduced this file was commit d70080c4 (from 2012).

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Alex Bennée
d6db2a1cdf docker: add debian-buster-arm64-cross
We can't build QEMU with this but we can use this image to build newer
arm64 testcases which need more up to date tools.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-08 17:32:35 +00:00
Richard Henderson
06bf3b153a tests/tcg/aarch64: Add pauth smoke test
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190201195404.30486-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05 16:52:39 +00:00
Aleksandar Markovic
dcca150f83 tests: tcg: mips: Remove old directories
Remove old test directories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Aleksandar Markovic
5e0aa63b08 tests: tcg: mips: Add two new Makefiles
Add Makefiles for two new direcitories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Aleksandar Markovic
073d9f2ce0 tests: tcg: mips: Move source files to new locations
MIPS TCG test will be organized by ISAs and ASEs in future.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Paolo Bonzini
7d37435bd5 avoid TABs in files that only contain a few
Most files that have TABs only contain a handful of them.  Change
them to spaces so that we don't confuse people.

disas, standard-headers, linux-headers and libdecnumber are imported
from other projects and probably should be exempted from the check.
Outside those, after this patch the following files still contain both
8-space and TAB sequences at the beginning of the line.  Many of them
have a majority of TABs, or were initially committed with all tabs.

    bsd-user/i386/target_syscall.h
    bsd-user/x86_64/target_syscall.h
    crypto/aes.c
    hw/audio/fmopl.c
    hw/audio/fmopl.h
    hw/block/tc58128.c
    hw/display/cirrus_vga.c
    hw/display/xenfb.c
    hw/dma/etraxfs_dma.c
    hw/intc/sh_intc.c
    hw/misc/mst_fpga.c
    hw/net/pcnet.c
    hw/sh4/sh7750.c
    hw/timer/m48t59.c
    hw/timer/sh_timer.c
    include/crypto/aes.h
    include/disas/bfd.h
    include/hw/sh4/sh.h
    libdecnumber/decNumber.c
    linux-headers/asm-generic/unistd.h
    linux-headers/linux/kvm.h
    linux-user/alpha/target_syscall.h
    linux-user/arm/nwfpe/double_cpdo.c
    linux-user/arm/nwfpe/fpa11_cpdt.c
    linux-user/arm/nwfpe/fpa11_cprt.c
    linux-user/arm/nwfpe/fpa11.h
    linux-user/flat.h
    linux-user/flatload.c
    linux-user/i386/target_syscall.h
    linux-user/ppc/target_syscall.h
    linux-user/sparc/target_syscall.h
    linux-user/syscall.c
    linux-user/syscall_defs.h
    linux-user/x86_64/target_syscall.h
    slirp/cksum.c
    slirp/if.c
    slirp/ip.h
    slirp/ip_icmp.c
    slirp/ip_icmp.h
    slirp/ip_input.c
    slirp/ip_output.c
    slirp/mbuf.c
    slirp/misc.c
    slirp/sbuf.c
    slirp/socket.c
    slirp/socket.h
    slirp/tcp_input.c
    slirp/tcpip.h
    slirp/tcp_output.c
    slirp/tcp_subr.c
    slirp/tcp_timer.c
    slirp/tftp.c
    slirp/udp.c
    slirp/udp.h
    target/cris/cpu.h
    target/cris/mmu.c
    target/cris/op_helper.c
    target/sh4/helper.c
    target/sh4/op_helper.c
    target/sh4/translate.c
    tcg/sparc/tcg-target.inc.c
    tests/tcg/cris/check_addo.c
    tests/tcg/cris/check_moveq.c
    tests/tcg/cris/check_swap.c
    tests/tcg/multiarch/test-mmap.c
    ui/vnc-enc-hextile-template.h
    ui/vnc-enc-zywrle.h
    util/envlist.c
    util/readline.c

The following have only TABs:

    bsd-user/i386/target_signal.h
    bsd-user/sparc64/target_signal.h
    bsd-user/sparc64/target_syscall.h
    bsd-user/sparc/target_signal.h
    bsd-user/sparc/target_syscall.h
    bsd-user/x86_64/target_signal.h
    crypto/desrfb.c
    hw/audio/intel-hda-defs.h
    hw/core/uboot_image.h
    hw/sh4/sh7750_regnames.c
    hw/sh4/sh7750_regs.h
    include/hw/cris/etraxfs_dma.h
    linux-user/alpha/termbits.h
    linux-user/arm/nwfpe/fpopcode.h
    linux-user/arm/nwfpe/fpsr.h
    linux-user/arm/syscall_nr.h
    linux-user/arm/target_signal.h
    linux-user/cris/target_signal.h
    linux-user/i386/target_signal.h
    linux-user/linux_loop.h
    linux-user/m68k/target_signal.h
    linux-user/microblaze/target_signal.h
    linux-user/mips64/target_signal.h
    linux-user/mips/target_signal.h
    linux-user/mips/target_syscall.h
    linux-user/mips/termbits.h
    linux-user/ppc/target_signal.h
    linux-user/sh4/target_signal.h
    linux-user/sh4/termbits.h
    linux-user/sparc64/target_syscall.h
    linux-user/sparc/target_signal.h
    linux-user/x86_64/target_signal.h
    linux-user/x86_64/termbits.h
    pc-bios/optionrom/optionrom.h
    slirp/mbuf.h
    slirp/misc.h
    slirp/sbuf.h
    slirp/tcp.h
    slirp/tcp_timer.h
    slirp/tcp_var.h
    target/i386/svm.h
    target/sparc/asi.h
    target/xtensa/core-dc232b/xtensa-modules.inc.c
    target/xtensa/core-dc233c/xtensa-modules.inc.c
    target/xtensa/core-de212/core-isa.h
    target/xtensa/core-de212/xtensa-modules.inc.c
    target/xtensa/core-fsf/xtensa-modules.inc.c
    target/xtensa/core-sample_controller/core-isa.h
    target/xtensa/core-sample_controller/xtensa-modules.inc.c
    target/xtensa/core-test_kc705_be/core-isa.h
    target/xtensa/core-test_kc705_be/xtensa-modules.inc.c
    tests/tcg/cris/check_abs.c
    tests/tcg/cris/check_addc.c
    tests/tcg/cris/check_addcm.c
    tests/tcg/cris/check_addoq.c
    tests/tcg/cris/check_bound.c
    tests/tcg/cris/check_ftag.c
    tests/tcg/cris/check_int64.c
    tests/tcg/cris/check_lz.c
    tests/tcg/cris/check_openpf5.c
    tests/tcg/cris/check_sigalrm.c
    tests/tcg/cris/crisutils.h
    tests/tcg/cris/sys.c
    tests/tcg/i386/test-i386-ssse3.c
    ui/vgafont.h

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20181213223737.11793-3-pbonzini@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Eric Blake <eblake@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-11 15:46:56 +01:00
Paolo Bonzini
72e21db7ea remove space-tab sequences
There are not many, and they are all simple mistakes that ended up
being committed.  Remove them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20181213223737.11793-2-pbonzini@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-11 15:46:55 +01:00
Fredrik Noring
19749a21d7 tests/tcg: mips: Test R5900 three-operand MADDU1
Test R5900 three-operand MADDU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
8e2e5e7dac tests/tcg: mips: Test R5900 three-operand MADDU
Test R5900 three-operand MADDU.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
84dc071236 tests/tcg: mips: Test R5900 three-operand MADD1
Test R5900 three-operand MADD1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
50f299da62 tests/tcg: mips: Test R5900 three-operand MADD
Test R5900 three-operand MADD.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
fabrice.desclaux@cea.fr
82c48fb79d Fixes i386 xchgq test
As "xchg" reads and writes both operands, the "+m" is required to avoid
undefined behavior on -O2 compilation.

Signed-off-by: Fabrice Desclaux <fabrice.desclaux@cea.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <03506cf0-a204-f619-8ee4-4990a5e69af5@cea.fr>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-11 18:41:25 +01:00
Laurent Vivier
1f442da51e tests/tcg/multiarch: fix 32bit linux-test on 64bit host
Fix:

  TEST    linux-test on i386
  .../tests/tcg/multiarch/linux-test.c:201: readdir

readdir() calls getdents64() to have the list of the entries in a
directory, and getdents64() can return 64bit d_off values (with ext4,
for instance) that will not fit in the 32bit d_off field of the
readdir() dirent structure.

To avoid that, use readdir64() to use a 64bit d_off field too.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-11-14 11:07:06 +00:00
Stefan Weil
e50a61219f tests: Fix typos in comments and help message (found by codespell)
Fix also a grammar issue.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20180713054755.23323-1-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26 17:17:32 +02:00
Cleber Rosa
8c9a895aaf tests/tcg/README: fix location for lm32 tests
Point to the right and obvious location for lm32 tests.

Signed-off-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20181004161852.11673-3-crosa@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26 17:17:32 +02:00
Fredrik Noring
35eb9be6bb tests/tcg/mips: Add tests for R5900 DIVU1
Add a test for DIVU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
990aa328be tests/tcg/mips: Add tests for R5900 DIV1
Add a test for DIV1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
4d261a6a59 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
Add a test for MTLO1 and MTHI1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
3303f017ad tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
Add a test for MFLO1 and MFHI1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
bec4d66b24 tests/tcg/mips: Add tests for R5900 three-operand MULTU1
Add a test for MULTU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
cb56125eea tests/tcg/mips: Add tests for R5900 three-operand MULT1
Add a test for MULT1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
667eded270 tests/tcg/mips: Add tests for R5900 three-operand MULTU
Add a test for MULTU.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
9d35580a57 tests/tcg/mips: Add tests for R5900 three-operand MULT
Add a test for MULT.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Peter Maydell
8ca19bd882 target/xtensa updates:
- fix gdbstub register counts;
 - add big-endian core test_kc705_be;
 - convert to do_transaction_failed and add test for failed memory
   transactions;
 - fix couple FPU2000 bugs;
 - fix s32c1i implementation;
 - clean up exception handlers generation in xtensa tests;
 - add support for semihosting console input through a chardev.
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Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging

target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transaction_failed and add test for failed memory
  transactions;
- fix couple FPU2000 bugs;
- fix s32c1i implementation;
- clean up exception handlers generation in xtensa tests;
- add support for semihosting console input through a chardev.

# gpg: Signature made Tue 18 Sep 2018 18:35:50 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180918-xtensa:
  target/xtensa: support input from chardev console
  target/xtensa: fix s32c1i TCGMemOp flags
  tests/tcg/xtensa: only generate defined exception handlers
  tests/tcg/xtensa: move exception handlers to separate section
  target/xtensa: fix FPU2000 bugs
  tests/tcg/xtensa: add test for failed memory transactions
  target/xtensa: convert to do_transaction_failed
  target/xtensa: add test_kc705_be core
  target/xtensa: clean up gdbstub register handling
  target/xtensa: fix gdbstub register counts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25 11:05:56 +01:00
Max Filippov
f68774ccd8 tests/tcg/xtensa: only generate defined exception handlers
Don't generate handlers for IRQ levels that are not defined for the CPU
or for window overflow/underflow exceptions for configs w/o windowed
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Max Filippov
f81aa02e0d tests/tcg/xtensa: move exception handlers to separate section
Not all CPU configurations may have enough space for handler code
between exception/interrupt vectors. Leave jumps to the handlers at the
vectors, but move all handlers past the vectors area.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Max Filippov
3ee01413be tests/tcg/xtensa: add test for failed memory transactions
Failed memory transactions should raise exceptions 14 (for fetch) or 15
(for load/store) with XEA2.

Memory accesses that result in TLB miss followed by an attempt to load
PTE from physical memory which fails should raise InstTLBMiss or
LoadStoreTLBMiss with XEA2.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Pavel Zbitskiy
3cea09271b target/s390x: fix PACK reading 1 byte less and writing 1 byte more
PACK fails on the test from the Principles of Operation: F1F2F3F4
becomes 0000234C instead of 0001234C due to an off-by-one error.
Furthermore, it overwrites one extra byte to the left of F1.

If len_dest is 0, then we only want to flip the 1st byte and never loop
over the rest. Therefore, the loop condition should be > and not >=.

If len_src is 1, then we should flip the 1st byte and pack the 2nd.
Since len_src is already decremented before the loop, the first
condition should be >=, and not >.

Likewise for len_src == 2 and the second condition.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-7-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
ad8c851d2e target/s390x: add EX support for TRT and TRTR
Improves "b213c9f5: target/s390x: Implement TRTR" by introducing the
intermediate functions, which are compatible with dx_helper type.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-6-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
478d360cd9 target/s390x: fix IPM polluting irrelevant bits
Suppose psw.mask=0x0000000080000000, cc=2, r1=0 and we do "ipm 1".
This command must touch only bits 32-39, so the expected output
is r1=0x20000000. However, currently qemu yields r1=0x20008000,
because irrelevant parts of PSW leak into r1 during program mask
transfer.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-5-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
dc95b31dac target/s390x: fix CSST decoding and runtime alignment check
CSST is defined as:

    C(0xc802, CSST,    SSF,   CASS, la1, a2, 0, 0, csst, 0)

It means that the first parameter is handled by in1_la1().
in1_la1() fills addr1 field, and not in1.

Furthermore, when extract32() is used for the alignment check, the
third parameter should specify the number of trailing bits that must
be 0. For FC these numbers are:

    FC=0 (word, 4 bytes):        2
    FC=1 (double word, 8 bytes): 3
    FC=2 (quad word, 16 bytes):  4

For SC these numbers correspond to the size:

    SC=0: 0
    SC=1: 1
    SC=2: 2
    SC=3: 3
    SC=4: 4

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-4-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
276ba120ed tests/tcg: add a simple s390x test
Copied from alpha.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-2-pavel.zbitskiy@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Alex Bennée
28cbb997d6 tests: add check_invalid_maps to test-mmap
This adds a test to make sure we fail properly for a 0 length mmap.
There are most likely other failure conditions we should also check.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: umarcor <1783362@bugs.launchpad.net>
Message-Id: <20180730134321.19898-3-alex.bennee@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-31 09:57:25 +02:00
Alex Bennée
1a3bdc6111 tests/tcg: remove runcom test
The combination of being rather esoteric and needing to support mmap @
0 means this only ever worked under translation. It has now regressed
even further and is no longer useful. Kill it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-24 11:45:25 +01:00
Alex Bennée
1a7fab926b tests: add top-level make dependency for docker builds
One problem with satisfying your docker dependencies in a sub-make it
you might end up trying to satisfy the dependency multiple times. This
is especially a problem with debian-sid based cross compilers and CI
setups. We solve this by doing a docker build pass at the top level
before any sub-makes are called.

We still need to satisfy dependencies in the Makefile.target call so
people can run tests from individual target directories. We introduce
a new Makefile.probe which gets called for each PROBE_TARGET and
allows us to build up the list. It does require multiply including
config-target.mak which shouldn't cause any issues as it shouldn't
define anything that clashes with config-host.mak. However we undefine
a few key variables each time around.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 22:13:32 +01:00
Alex Bennée
ab93256144 tests/tcg/i386: extend timeout for runcom test
The Travis hardware can be a little slow and the runcom test is fairly
heavy in calculating pi. Lets double the timeout so we don't trip up
during CI by mistake.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
83749e649e tests/tcg: override runners for broken tests
To get a clean run of check-tcg these tests are currently skipped:

  - hello-mips for mips
  - linux-test for sparc

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
607bf9b5a5 tests/tcg: add run, diff, and skip helper macros
As we aren't using the default runners for all the test cases it is
easy to miss out things like timeouts. To help with this we add some
helpers and use them so we only need to make core changes in one
place.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
c722a9e492 Makefile.target: add (clean-/build-)guest-tests targets
Now all the build infrastructure is in place we can build tests for
each guest that we support. That support mainly depends on having
cross compilers installed or docker setup. To keep all the logic for
that together we put the rules in tests/tcg/Makefile.include and
include it from the main Makefile.target.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
7e97017e7d tests/tcg/Makefile: update to be called from Makefile.target
This make is now invoked from each individual target make with the
appropriate CC and EXTRA_CFLAGS set for each guest. It then includes
additional Makefile.targets from:

  - tests/tcg/multiarch (always)
  - tests/tcg/$(TARGET_BASE_ARCH) (if available)
  - tests/tcg/$(TARGET_NAME)

The order is important as the later Makefile's may want to suppress
TESTS from its base arch profile. Each included Makefile.target is
responsible for adding TESTS as well as defining any special build
instructions for individual tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
97103c256e tests/tcg: enable building for PowerPC
Now we have restored debian-image-powerpc-cross using Debian SID
compilers we can build for 32 bit powerpc. Although PPC32 supports a
range of pages sizes currently only 4k works so the others are
commented out for now.

We can also merge the ppc64 support under the base architecture
directory to avoid too much proliferation of directories.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
e100a96755 tests/tcg: enable building for RISCV64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
33b2c4b50f tests/tcg: enable building for mips64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
cc6c7365b8 tests/tcg: enable building for sparc64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
a5ec3e36dc tests/tcg: enable building for sh4
As before, using Debian SID compilers. While the compiler can be
coerced into generating big-endian code it seems the linker can't deal
with it so we only enable the building for little endian SH4.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
21d71c8c41 tests/tcg: enable building for m68k
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
3ae8a1000b tests/tcg: enable building for HPPA
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
4f2cbcfb4d tests/tcg/alpha: add Alpha specific tests
These tests did use their own crt.o stub however that is a little
stone age so we drop crt.S and just statically link to the cross
compilers libraries.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
409c1c9cbd tests/tcg: enable building for Alpha
We can't use our normal Debian based compilers as Alpha isn't an
officially supported architecture. However it is available as a port
and fortunately cross compilers for all these targets are included in
Debian Sid, the perpetual rolling/unstable/testing version of Debian.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
1e2107092d tests/tcg: enable building for ppc64
Currently this just enables building the multiarch tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
78353f49d2 tests/tcg: enable building for s390x
This doesn't add any additional tests but enables building the
multiarch tests for s390x.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
2018-06-20 20:22:34 +01:00
Alex Bennée
2ac93f19b6 tests/tcg/mips: include common mips hello-mips
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
7086ffbb93 tests/tcg: enable building for MIPS
This doesn't add any additional tests but enables building the
multiarch tests for MIPS using docker cross compilers. We don't have a
cross compiler for mips64 big endian though.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
106ea2db12 tests/tcg: move MIPS specific tests into subdir
These only need to be built for MIPS guests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
8ec8a55e3f tests/tcg/arm: add fcvt test cases for AArch32/64
This runs through the usual float to float conversions and crucially
also runs with ARM Alternative Half Precision Format.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
29e0436e3d tests/tcg: enable building for AArch64
We only have compilers for the (default) little endian variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
65eab0f8cb tests/tcg/arm: fix up test-arm-iwmmxt test
We need to rename the source file to a .S so we can do a single-line
assemble and link invocation. We also specify the additional CFLAGS
for the compile as it's a non-standard ARM binary.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[rth: force fpu configuration]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
ab4aac5023 tests/tcg: enable building for ARM
This allows us to use the docker cross compiler image to build these
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
c348722c53 tests/tcg: move ARM specific tests into subdir
These only need to be built for ARM guests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
e571ba67cb tests/tcg/i386/test-i386: fix printf format
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
9b8381d1ed tests/tcg/i386/test-i386: use modern vector_size attributes
The compiler complains about the old __mode__ style attributes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
3a082ec01b tests/tcg/x86_64: add Makefile.target
The sources for x86_64 are shared in the i386 directory which will be
included thanks to TARGET_BASE_ARCH. However not all sources build so
we need to filter out the ones we can't build in the 64 bit world and
those that can't be built for 32 bit.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
25f9e7e8d7 tests/tcg/i386: add runner for test-i386-fprem
The runner needs to compare against a reference run. We also only run
this test when SPEED=slow as it takes a while.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
9ae02bf889 tests/tcg/i386: fix test-i386
We don't include anything from qemu itself for the build.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Fam Zheng
553a5a6046 tests/tcg/i386: Build fix for hello-i386
We have -Werror=missing-prototype, add a dummy prototype to avoid that
warning.

Signed-off-by: Fam Zheng <famz@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
8b17219e7d tests/tcg: enable building for i386
While you can construct a compile command that does work using the
x86_64 host compiler that most people use this is flakey. Different
distros handle this is different ways so we default to using a known
good i386 compiler via docker.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
4132431f24 tests/tcg: move i386 specific tests into subdir
These only need to be built for i386 guests. This includes a stub
tests/tcg/i386/Makfile.target which absorbs some of what was in
tests/tcg/Makefile.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
07c85b696a tests/tcg/multiarch: move most output to stdout
The default test run outputs to stdout so it can be re-directed.
Errors are still reported to stderr.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
2018-06-20 20:22:34 +01:00
Alex Bennée
5aa632d5d9 tests/tcg/multiarch: don't hard code paths/ports for linux-test
The fixed path and ports get in the way of running our tests and
builds in parallel. Instead of using TESTPATH we use mkdtemp() and
instead of a fixed port we allow the kernel to assign one and query it
afterwards.

Ideally test directory creation should be common functionally across
all TCG tests but this could complicate an already huge patch series
so we mark it as a TODO for next time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
875fcce661 tests/tcg/multiarch: enable additional linux-test tests
Un-comment the remaining tests.

I removed the itimer value tests because I'm fairly sure a re-arming
timer will always have a different value in it when you grab it.

I've also fixed up the clone thread flags as QEMU will only allow a
clone to use flags which match glibc. However the test is still racey
so it remains disabled by default - it can be run by passing any
additional parameters on the command line.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Fam Zheng
5e13cbd51d tests/tcg/multiarch: Build fix for linux-test
To keep the compiler happy, and to fit in our buildsys flags:

- Make local functions "static"
- #ifdef out unused functions
- drop cutils/osdep dependencies

Signed-off-by: Fam Zheng <famz@redhat.com>
[AJB: drop cutils/osdep dependencies]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
dd28bebd02 tests/tcg: move architecture independent tests into subdir
We will want to build these for all supported guest architectures so
lets move them all into one place. We also drop test_path at this
point because it needs qemu utils and glib bits which is hard to
support for cross compiling.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Max Filippov
d0ce7e9cfc target/xtensa: fix timers test
The value of CCOUNT special register is calculated as time elapsed
since CCOUNT == 0 multiplied by the core frequency. In icount mode time
increment between consecutive instructions that don't involve time
warps is constant, but unless the result of multiplication of this
constant by the core frequency is a whole number the CCOUNT increment
between these instructions may not be constant. E.g. with icount=7 each
instruction takes 128ns, with core clock of 10MHz CCOUNT values for
consecutive instructions are:

  502: (128 * 502 * 10000000) / 1000000000 = 642.56
  503: (128 * 503 * 10000000) / 1000000000 = 643.84
  504: (128 * 504 * 10000000) / 1000000000 = 645.12

I.e.the CCOUNT increments depend on the absolute time. This results in
varying CCOUNT differences for consecutive instructions in tests that
involve time warps and don't set CCOUNT explicitly.

Change frequency of the core used in tests so that clock cycle takes
exactly 64ns. Change icount power used in tests to 6, so that each
instruction takes exactly 1 clock cycle. With these changes CCOUNT
increments only depend on the number of executed instructions and that's
what timer tests expect, so they work correctly.

Longer story:
  http://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg04326.html

Cc: Pavel Dovgaluk <Pavel.Dovgaluk@ispras.ru>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-03-26 14:17:04 -07:00
Eric Blake
2562755ee7 maint: Fix macros with broken 'do/while(0); ' usage
The point of writing a macro embedded in a 'do { ... } while (0)'
loop (particularly if the macro has multiple statements or would
otherwise end with an 'if' statement) is so that the macro can be
used as a drop-in statement with the caller supplying the
trailing ';'.  Although our coding style frowns on brace-less 'if':
  if (cond)
    statement;
  else
    something else;
that is the classic case where failure to use do/while(0) wrapping
would cause the 'else' to pair with any embedded 'if' in the macro
rather than the intended outer 'if'.  But conversely, if the macro
includes an embedded ';', then the same brace-less coding style
would now have two statements, making the 'else' a syntax error
rather than pairing with the outer 'if'.  Thus, even though our
coding style with required braces is not impacted, ending a macro
with ';' makes our code harder to port to projects that use
brace-less styles.

The change should have no semantic impact.  I was not able to
fully compile-test all of the changes (as some of them are
examples of the ugly bit-rotting debug print statements that are
completely elided by default, and I didn't want to recompile
with the necessary -D witnesses - cleaning those up is left as a
bite-sized task for another day); I did, however, audit that for
all files touched, all callers of the changed macros DID supply
a trailing ';' at the callsite, and did not appear to be used
as part of a brace-less conditional.

Found mechanically via: $ git grep -B1 'while (0);' | grep -A1 \\\\

Signed-off-by: Eric Blake <eblake@redhat.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20171201232433.25193-7-eblake@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-16 14:54:52 +01:00
Max Filippov
e55239e2b6 target/xtensa: tests: fix memctl SR test
memctl SR is not available on dc232b, as it was introduced in more
recent hardware release. Now that this information is available through
the libisa the test fails. Fix the test.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-01-09 09:55:38 -08:00
Khem Raj
04b33e2186 Replace 'struct ucontext' with 'ucontext_t' type
glibc used to have:

   typedef struct ucontext { ... } ucontext_t;

glibc now has:

   typedef struct ucontext_t { ... } ucontext_t;

(See https://sourceware.org/bugzilla/show_bug.cgi?id=21457
 for detail and rationale for the glibc change)

However, QEMU used "struct ucontext" in declarations. This is a
private name and compatibility cannot be guaranteed. Switch to
only using the standardized type name.

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Message-id: 20170628204452.41230-1-raj.khem@gmail.com
Cc: Kamil Rytarowski <kamil@netbsd.org>
Cc: Riku Voipio <riku.voipio@iki.fi>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
[PMM: Rewrote commit message, based mostly on the one from
 Nathaniel McCallum]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20 10:10:28 +01:00
Eric Blake
b43671f80c tests: Avoid non-portable 'echo -ARG'
POSIX says that backslashes in the arguments to 'echo', as well as
any use of 'echo -n' and 'echo -e', are non-portable; it recommends
people should favor 'printf' instead.  This is definitely true where
we do not control which shell is running (such as in makefile snippets
or in documentation examples).  But even for scripts where we
require bash (and therefore, where echo does what we want by default),
it is still possible to use 'shopt -s xpg_echo' to change bash's
behavior of echo.  And setting a good example never hurts when we are
not sure if a snippet will be copied from a bash-only script to a
general shell script (although I don't change the use of non-portable
\e for ESC when we know the running shell is bash).

Replace 'echo -n "..."' with 'printf %s "..."', and 'echo -e "..."'
with 'printf %b "...\n"', with the optimization that the %s/%b
argument can be omitted if the string being printed is a strict
literal with no '%', '$', or '`' (we could technically also make
this optimization when there are $ or `` substitutions but where
we can prove their results will not be problematic, but proving
that such substitutions are safe makes the patch less trivial
compared to just being consistent).

In the qemu-iotests check script, fix unusual shell quoting
that would result in word-splitting if 'date' outputs a space.

In test 051, take an opportunity to shorten the line.

In test 068, get rid of a pointless second invocation of bash.

CC: qemu-trivial@nongnu.org
Signed-off-by: Eric Blake <eblake@redhat.com>
Message-id: 20170703180950.9895-1-eblake@redhat.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2017-07-11 17:45:00 +02:00
Richard Henderson
4a09d0bb34 target/openrisc: Rename the cpu from or32 to or1k
This is in keeping with the toolchain and or1ksim.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-14 08:14:58 +11:00
Max Filippov
8b912ff033 target/xtensa: tests: clean up interrupt tests
Don't use hardcoded software interrupt masks, use XCHAL macros.
Mask off timer interrupt bits that are not checked for.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:36:09 -08:00
Max Filippov
255d254382 target/xtensa: tests: add memctl test
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
0a362d0768 target/xtensa: tests: add ccount write tests
Check that CCOUNT SR is writable and that CCOMPARE timers are updated
when CCOUNT is written to.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
4f89b41c28 target/xtensa: tests: replace hardcoded interrupt masks
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
72b3b8f24a target/xtensa: tests: fix timer tests
Don't expect that CCOUNT increments are equal to the number of executed
instructions. Verify that timer interrupt does not fire before the
programmed CCOMPARE value and does fire after.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
122d302053 target/xtensa: tests: run tests with icount
Timer tests expect certain determinism in CCOUNT updates and timer
interrupts firing. Run QEMU with -icount to get deterministic results.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Thomas Huth
fcf5ef2ab5 Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00
Paolo Bonzini
03514ac25c test-i386: fix bitrot for 64-bit
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-10-24 15:27:19 +02:00
Paolo Bonzini
72bd94c578 qemu-tech: move TCG test documentation to tests/tcg/README
Reviewed-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-10-07 10:05:30 +02:00
Rabin Vincent
4a58f35b79 tests: cris: add v17 ADDC test
Add a test for the newly implemented ADDC instruction in the v17 CRIS
CPU.

Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 11:32:06 +02:00
Rabin Vincent
85b3ed1db5 tests: cris: remove check_time1
This test, borrowed from the GDB simulator test suite, checks that every
syscall increments the time returned by gettimeofday() by exactly 1 ms.
This is not guaranteed or even desirable on QEMU so remove this test.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 10:48:07 +02:00
Rabin Vincent
d10a0102b3 tests: cris: remove openpf4 test
This test, borrowed from the GDB simulator test suite, is meant to test
the GDB simulator's --sysroot feature and always fails in QEMU.  Remove
it.  openpf3 tests the same sequence of system calls (without assuming
the precence of --sysroot).

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 10:48:01 +02:00
Rabin Vincent
f278d5cbe5 tests: cris: fix syscall inline asm
Add the appropriate register constraints for the inline asm for the
write and exit system calls.  Without the correct constraints for the
write() function, correct failure messages are not printed succesfully
on newer version of GCC.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 10:47:21 +02:00
Rabin Vincent
21ce148c7e tests: cris: force inlining
The CRIS tests expect that functions marked inline are always inline.
With newer versions of GCC, building them results warnings like the
following and spurious failures when they are run.

In file included from tests/tcg/cris/check_moveq.c:5:0:
tests/tcg/cris/crisutils.h:66:20: warning: inlining failed in call to
'cris_tst_cc.constprop.0': call is unlikely and code size would grow [-Winline]
tests/tcg/cris/check_moveq.c:28:13: warning: called from here [-Winline]

Use the always_inline attribute when building them to fix this.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Rabin Vincent <rabinv@axis.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-09-28 10:45:44 +02:00
Markus Armbruster
a9c94277f0 Use #include "..." for our own headers, <...> for others
Tracked down with an ugly, brittle and probably buggy Perl script.

Also move includes converted to <...> up so they get included before
ours where that's obviously okay.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Tested-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12 16:19:16 +02:00
Stefan Weil
cb8d4c8f54 Fix some typos found by codespell
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-05-18 15:04:27 +03:00
Veronia Bahaa
f348b6d1a5 util: move declarations out of qemu-common.h
Move declarations out of qemu-common.h for functions declared in
utils/ files: e.g. include/qemu/path.h for utils/path.c.
Move inline functions out of qemu-common.h and into new files (e.g.
include/qemu/bcd.h)

Signed-off-by: Veronia Bahaa <veroniabahaa@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-22 22:20:17 +01:00
Markus Armbruster
c80f6e9caa Clean up includes some more
Manually drop redundant includes that scripts/clean-includes misses,
e.g. because they're hidden in generator programs, or they use the
wrong kind of delimiter.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-22 22:20:16 +01:00
Daniel P. Berrange
1618d2ae7f maint: remove unused include for signal.h
A number of files were including signal.h but not using any
of the functions it provides

Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-09-11 10:21:38 +03:00
Max Filippov
85d36377e4 target-xtensa: test cross-page opcode
Alter cross-page TB test to also test cross-page opcode.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-12-17 05:49:32 +03:00
Max Filippov
09c7fbef76 target-xtensa: add entry overflow test
Check that entry instruction raises window overflow exception when
PS.CALLINC points to live registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-10 17:59:13 +03:00
Max Filippov
20303e42d4 target-xtensa: tests: pre-process tests linker script
Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
core configuration. Instead of hard-coding dc232 defaults pull endianness,
number of high-priority interrupts and location of vectors from the core
configuration and pass it through the C preprocessor.

While at it clean up tabs and align the initial stack on 16 bytes.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03 00:51:43 +03:00
Peter Maydell
adbfc34103 Xtensa fixes queue 2014-05-26:
- fix cross-page jumps/calls at the end of TB;
 - add tests for TBs and instructions crossing page boundary.
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Merge remote-tracking branch 'remotes/xtensa/tags/20140526-xtensa' into staging

Xtensa fixes queue 2014-05-26:
- fix cross-page jumps/calls at the end of TB;
- add tests for TBs and instructions crossing page boundary.

# gpg: Signature made Mon 26 May 2014 09:37:39 BST using RSA key ID F83FA044
# gpg: Can't check signature: public key not found

* remotes/xtensa/tags/20140526-xtensa:
  target-xtensa: add tests for cross-page TB
  target-xtensa: completely clean TLB between MMU tests
  target-xtensa: fix cross-page jumps/calls at the end of TB

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-28 14:47:35 +01:00
Max Filippov
57a740514d target-xtensa: add tests for cross-page TB
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26 12:33:54 +04:00
Max Filippov
ca3164df4d target-xtensa: completely clean TLB between MMU tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26 12:33:54 +04:00
Michael Walle
4e7d30a22a test: lm32: use semihosting for testing
Instead of the lm32-sys device, use semihosting to print to the host
console and exit the test.

Signed-off-by: Michael Walle <michael@walle.cc>
2014-05-24 19:42:29 +02:00
Michael Walle
a946ce8020 test: lm32: make test cases independent
Make test cases independent from from each other. Eg. if a test case needs
a specific value in register A, don't rely on the fact that it is already
set by the preceding test case.

Signed-off-by: Michael Walle <michael@walle.cc>
2014-05-24 19:42:29 +02:00
Peter Maydell
ad0a118fa3 tests/tcg: Fix compilation of test_path
The test_path binary is (unlike the other test binaries in tests/tcg)
actually intended to be compiled with the same compiler used to build
the main QEMU executables. It actually #includes a number of the
QEMU source files in an attempt to unit-test the util/path.c functions,
and so if it is not compiled with the same compiler used by configure
to set CONFIG_ settings then it is liable to fail to build.
Fix the makefile to build it with the default C compiler rules, not
CC_I386, and fix the test itself not to include a lot of unnecessary
trace related source files which cause the build to fail if the trace
backend is anything other than 'simple'.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-05-07 21:00:43 +04:00
Stefan Weil
6d4adef48d tests: Fix 'make test' for i686 hosts (build regression)
'make test' is broken at least since commit
baacf04799. Several source files were moved
to util/, and some of them there split, so add the missing prefix and new
files to fix the compiler and linker errors.

There remain more issues, but these changes allow running the test on a
Linux i686 host.

Cc: qemu-stable@nongnu.org
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-15 13:54:18 +04:00
Max Filippov
2c09eee112 target-xtensa: add basic tests for cache opcodes
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:02 +04:00
Max Filippov
a2e67072b7 target-xtensa: allow using core configuration in tests
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Max Filippov
d0fa1f0df3 target-xtensa: add overridable test_init macro
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24 04:47:01 +04:00
Michael Walle
f40c49ac9f tests: lm32: new rule for single test cases
Introduce new target "check_%" to run individual test caes, eg.
  make check_mmu

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-04 19:34:29 +01:00
Sebastian Macke
14a650ec25 target-openrisc: Correct carry flag check of l.addc and l.addic test cases
The test cases did not correctly test for the carry flag.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
Reviewed-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Jia Liu <proljc@gmail.com>
2013-11-20 21:47:46 +08:00
Anthony Liguori
64160cd2a3 xtensa queue 2013-07-29
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Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging

xtensa queue 2013-07-29

* filippov/tags/20130729-xtensa:
  target-xtensa: check register window inline
  target-xtensa: don't generate dead code to access invalid SRs
  tests/tcg/xtensa: Fix out-of-tree build
  target-xtensa: avoid double-stopping at breakpoints
  target-xtensa: add fallthrough markers
  target-xtensa: add extui unit test

Conflicts:
	configure

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-08-05 08:06:25 -05:00
Petar Jovanovic
beb3faaa00 target-mips: correct the values in the DSP tests
Five tests files for DSP instructions had wrong expected values in the tests.
This change fixes this, and this has been cross-checked by running the same
test binaries on Malta 74K board.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-30 17:48:24 +02:00
Andreas Färber
aaa2ebc567 tests/tcg/xtensa: Fix out-of-tree build
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:35:45 +04:00
Max Filippov
7be9d0e6d1 target-xtensa: add extui unit test
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29 18:24:26 +04:00
Petar Jovanovic
b6a9f4682e target-mips: fix mipsdsp_mul_q31_q31
Multiplication of two fractional word elements is not correct when sign
extension/promotion is needed. This change fixes it by adding correct
casts from unsigned to signed values.
In addition, the tests (dpaq_sa_l_w.c and dpsq_sa_l_w.c) have been extended
to trigger the current issue.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29 07:48:17 +02:00
Petar Jovanovic
d36c231f4b target-mips: fix mipsdsp_trunc16_sat16_round
This change corrects rounding and saturation of Q31 fractional value in
mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the
corner case for PRECRQ_RS.PH, and this test case is also part of the change.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29 00:27:36 +02:00
Petar Jovanovic
4877866ee4 target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15
Multiplication of Q15 fractional halfword vectors was incorrect in the
previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take
element signs into account. This change fixes it, and it adds a test case
for it.

The change also removes unnecessary cast in the function
mipsdsp_mul_q15_q15_overflowflag21().

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Richard Henderson  <rth@twiddle.net> 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28 18:26:36 +02:00
Anthony Liguori
95de21a430 Merge remote-tracking branch 'mjt/trivial-patches' into staging
# By Christophe Lyon (1) and others
# Via Michael Tokarev
* mjt/trivial-patches:
  target-moxie: replace target_phys_addr_t with hwaddr
  Rename hexdump to avoid FreeBSD libutil conflict
  remove some double-includes
  translate: remove redundantly included qemu/timer.h
  Remove twice include of qemu-common.h
  fix /proc/self/maps output

Message-id: 51977B44.1000302@msgid.tls.msk.ru
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-22 08:22:36 -05:00
Petar Jovanovic
0ba365f4a9 target-mips: fix EXTPDP and setting up pos field in the DSPControl reg
This change makes sure that modifications of pos field in the DSPControl
register do not trash other bits in the register. This bug can be triggered
with the additional test case in mips32-dsp/extpdp.c in this commit.

In addition to this, this change corrects incorrect calculation of the mask
for EXTPDP.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-19 15:10:51 +02:00
Michael Tokarev
997aba8e25 remove some double-includes
Some source files #include the same header more than
once for no good reason.  Remove second #includes in
such cases.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-18 16:35:12 +04:00
Petar Jovanovic
489ed4bbae target-mips: fix incorrect behaviour for EXTP
The mask for EXTP instruction when size=31 has not been correctly
calculated.

The test (mips32-dsp/extp.c) has been extended to include the case that
triggers the issue.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-17 19:29:40 +02:00
Petar Jovanovic
c0f5f9ce86 target-mips: fix incorrect behaviour for INSV
Corner case for INSV instruction when size=32 has not been correctly
implemented. The mask for size should be one bit wider, and preparing the
filter variable should be aware of this case too.

The test for INSV has been extended to include the case that triggers the
bug.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-08 18:46:38 +02:00
Petar Jovanovic
29851ee7c8 target-mips: fix calculation of overflow for SHLL.PH and SHLL.QB
This change corrects and simplifies how discard is calculated for shift
left logical vector instructions. It is used to detect overflow and set bit
22 in the DSPControl register.

The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases
that expose incorrectness in the previous implementation.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03 11:50:49 +02:00
Petar Jovanovic
b1ca31d7ce target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHR
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format.
Otherwise, the results are unpredictable. Once the operands were corrected
in the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became
visible.

This change corrects the tests for MAQ_SA_W.PHL/MAQ_SA_W.PHR and fixes
sign-related issue in mipsdsp_mul_q15_q15. It also removes unnecessary
comment.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
2013-04-15 16:07:57 +02:00
Michael Walle
6036e9d87e tests: tcg: lm32: add more test cases
Esp. for testing zero/sign extend in compare operations.

Signed-off-by: Michael Walle <michael@walle.cc>
2013-03-18 19:40:34 +01:00
Petar Jovanovic
8b758d0568 target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
Fix for rndrashift_short_acc to set correct value to higher 64 bits.
This change also corrects conditions when bit 23 of the DSPControl register
is set.

The existing test files have been extended with several examples that
trigger the issues. One bug/example in the test file for EXTR_RS_W has been
found and reported by Klaus Peichl.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-17 01:06:34 +01:00
Petar Jovanovic
20c334a797 target-mips: fix DSP overflow macro and affected routines
The previous implementation incorrectly used same macro to detect overflow
for addition and subtraction. This patch makes distinction between these
two, and creates separate macros. The affected routines are changed
accordingly.

This change also includes additions to the existing tests for SUBQ_S_PH and
SUBQ_S_W that would trigger the fixed issue, and it removes dead code from
the test file. The last test case in subq_s_w.c is a bug found/reported/
isolated by Klaus Peichl from Dolby.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-04 18:15:34 +01:00
Petar Jovanovic
a345481baa target-mips: fix for sign-issue in MULQ_W helper
Correct sign-propagation before multiplication in MULQ_W helper.
The change also fixes previously incorrect expected values in the
tests for MULQ_RS.W and MULQ_S.W.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23 22:20:45 +01:00
Petar Jovanovic
9c19eb1e20 target-mips: fix for incorrect multiplication with MULQ_S.PH
The change corrects sign-related issue with MULQ_S.PH. It also includes
extension to the already existing test which will trigger the issue.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23 22:20:44 +01:00
Paolo Bonzini
1b99f83e39 test-i386: make it compile with a recent gcc
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18 15:03:55 -08:00
Paolo Bonzini
40475087a5 test-i386: QEMU_PACKED is not defined here
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18 15:03:54 -08:00
Petar Jovanovic
e62a214cd4 target-mips: fix incorrect test for MTHLIP
The pos field in the DSPControl register is not correctly initialized.
Per documentation, the result of MTHLIP is unpredictable if the value of the
pos field before the execution is greater than 32.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-31 23:42:04 +01:00
Petar Jovanovic
da1a4cef9e target-mips: Fix helper and tests for dot/cross-dot product instructions
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly
defines halfword vector elements as unsigned values. This results in wrong
output which is not triggered in the tests as they also follow this logic.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-08 11:58:43 +01:00
Petar Jovanovic
b8abbbe8df target-mips: Fix for helpers for EXTR_* instructions
The change removes some unnecessary and incorrect code for EXTR_S.H.
Further, it corrects the mask for shift value in the EXTR_ instructions. It also
extends the existing tests so they trigger the issues corrected with the change.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01 11:11:38 +01:00
Petar Jovanovic
eec8972a5b target-mips: Fix incorrect reads and writes to DSPControl register
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in
the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32
these bits must be written as zero, and return zero on read.

The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes
the tests that use these instructions, and makes them smaller and simpler.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01 11:10:47 +01:00
Paolo Bonzini
1de7afc984 misc: move include files to include/qemu/
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:32:39 +01:00
Paolo Bonzini
cb9c377f54 janitor: add guards to headers
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19 08:31:31 +01:00
Max Filippov
5dacd229eb target-xtensa: add s32c1i unit tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 18:48:26 +00:00
Max Filippov
efdfac94f4 target-xtensa: add SR accessibility unit tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08 18:48:26 +00:00
Petar Jovanovic
19e6c50d2d target-mips: Fix incorrect shift for SHILO and SHILOV
helper_shilo has not been shifting an accumulator value correctly for negative
values in 'shift' field. Minor optimization for shift=0 case.
This change also adds tests that will trigger issue and check for regressions.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-06 08:12:14 +01:00
Petar Jovanovic
34f5606ee1 target-mips: Fix incorrect code and test for INSV
Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-06 08:10:50 +01:00
Catalin Patulea
a9523d14c4 tests/tcg: new test for i386 FPREM and FPREM1
This is setting the stage for a cleanup of FPREM and FPREM1 helpers while being
sure that they behave same as bare metal.

The test constructs operands using combinations of corner cases for the
floating-point bitfields and prints operands, result and FPU status word for
FPREM and FPREM1. The outputs can then be compared between bare metal and QEMU.
The 'run-test-i386-fprem' make target does just that.

Signed-off-by: Catalin Patulea <catalinp@google.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-11-10 13:49:05 +00:00
Jia Liu
d70080c4e3 target-mips: Add ASE DSP testcases
Add MIPS ASE DSP testcases.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 21:37:21 +01:00
Catalin Patulea
f71d61216e tests/tcg: fix unused result warnings
With i386-linux-user target on x86_64 host, this does not introduce any new test
failures.

Signed-off-by: Catalin Patulea <catalinp@google.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-30 18:55:02 +00:00
Catalin Patulea
49cdaea18b tests/tcg: fix a few warnings
Signed-off-by: Catalin Patulea <catalinp@google.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-27 14:37:25 +00:00
Catalin Patulea
f62cb1b6dd tests/tcg: fix build
This broke when the tests were moved from tests/ to tests/tcg/.

On x86_64 host/i386-linux-user non-kvm guest, test-i386 and test-mmap are broken, but at least they build.

To build/run the tests:
$ cd $BUILD_PATH/tests/tcg
$ SRC_PATH=path/to/qemu make <target>

Signed-off-by: Catalin Patulea <catalinp@google.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-19 20:40:21 +02:00
Jia Liu
d901eff3e6 target-or32: Add testcases
Add testcases for OpenRISC.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:06 +00:00
Max Filippov
c305e32f43 target-xtensa: add MMU pagewalking tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-09 10:45:03 +00:00
Jim Meyering
a31f053129 fix some common typos
These were identified using: http://github.com/lyda/misspell-check
and run like this to create a bourne shell script using GNU sed's
-i option:

git ls-files|grep -vF .bin | misspellings -f - |grep -v '^ERROR:' |perl \
-pe 's/^(.*?)\[(\d+)\]: (\w+) -> "(.*?)"$/sed -i '\''${2}s!$3!$4!'\'' $1/'

Manually eliding the FP, "rela->real" and resolving "addres" to
address (not "adders") we get this:

  sed -i '450s!thru!through!' Changelog
  sed -i '260s!neccessary!necessary!' coroutine-sigaltstack.c
  sed -i '54s!miniscule!minuscule!' disas.c
  sed -i '1094s!thru!through!' hw/usb/hcd-ehci.c
  sed -i '1095s!thru!through!' hw/usb/hcd-ehci.c
  sed -i '21s!unecessary!unnecessary!' qapi-schema-guest.json
  sed -i '307s!explictly!explicitly!' qemu-ga.c
  sed -i '490s!preceeding!preceding!' qga/commands-posix.c
  sed -i '792s!addres!address!' qga/commands-posix.c
  sed -i '6s!beeing!being!' tests/tcg/test-mmap.c

Also, manually fix "arithmentic", spotted by Peter Maydell:

  sed -i 's!arithmentic!arithmetic!' coroutine-sigaltstack.c

Signed-off-by: Jim Meyering <meyering@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-05-14 07:27:24 +02:00
Max Filippov
536a98d4d6 target-xtensa: add tests for LOOPNEZ and LOOPGTZ
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:24:50 +00:00
Max Filippov
ad4ccc9370 target-xtensa: add test for IBREAK invalidation
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14 15:25:39 +00:00
Max Filippov
ec9fe93efe target-xtensa: add tests for LBEG/LEND invalidation
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-14 15:25:39 +00:00
Max Filippov
7d6b9f0a38 target-xtensa: improve unit tests debugging
- add testcase announcement;
- add global symbols for individual tests;
- add host-debug-* makefile target.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-04-14 03:48:08 +04:00
Michael Walle
927b241d66 tests: fix out-of-tree building for lm32 target
Signed-off-by: Michael Walle <michael@walle.cc>
2012-03-31 19:56:03 +02:00
Max Filippov
e7dfa64def target-xtensa: add breakpoint tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-20 20:07:12 +04:00
Edgar E. Iglesias
bee5a5fb11 cris: Update paths to match the move of tests/cris
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2012-01-13 11:09:56 +01:00