Commit Graph

451 Commits

Author SHA1 Message Date
Alex Bennée
380976f40f tests/tcg: ensure we re-configure if configure.sh is updated
We were only doing this if docker was enabled which isn't quite right.

Fixes: fc76c56d3f
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20191211170520.7747-17-alex.bennee@linaro.org>
2019-12-19 08:20:16 +00:00
Alex Bennée
afc3a8f9f1 configure: allow disable of cross compilation containers
Our docker infrastructure isn't quite as multiarch as we would wish so
lets allow the user to disable it if they want. This will allow us to
use still run check-tcg on non-x86 CI setups.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Cleber Rosa <crosa@redhat.com>
Tested-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Richard Henderson <richard.henderson@linaro.org>
2019-12-18 20:17:24 +00:00
Taylor Simpson
22c30b2d20 tests/tcg: modify multiarch tests to work with clang
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <1574032465-12186-1-git-send-email-tsimpson@quicinc.com>
[AJB: tweak header line]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-11-20 10:53:31 +00:00
Richard Henderson
3d72543494 tests/tcg/multiarch/linux-test: Fix error check for shmat
The error indicator for this syscall is -1, not 0.

Fixes: e374bfa35b ("shm tests - disabled clone test")
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20191106113318.10226-3-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-11-06 13:30:04 +01:00
Alex Bennée
3089e74e67 tests/tcg: enable plugin testing
If CONFIG_PLUGINS is enabled then lets enable testing for all our TCG
targets. This is a simple smoke test that ensure we don't crash or
otherwise barf out by running each plugin against each test.

There is a minor knock on effect for additional runners which need
specialised QEMU_OPTS which will also need to declare a plugin version
of the runner. If this gets onerous we might need to add another
helper.

Checking the results of the plugins is left for a later exercise.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28 15:12:38 +00:00
Alex Bennée
eba9ccf8f8 tests/tcg: drop test-i386-fprem from TESTS when not SLOW
This is a very slow running test which we only enable explicitly.
However having it in the TESTS lists would confuse additional tests
like the plugins test which want to run on all currently enabled
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28 15:12:38 +00:00
Alex Bennée
1852f3e486 tests/tcg: move "virtual" tests to EXTRA_TESTS
Otherwise clever expanders like the plugins test get unstuck.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28 15:12:38 +00:00
Alex Bennée
02f903140b tests/tcg: set QEMU_OPTS for all cris runs
This will important for ensuring the plugin test variants will also
work.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28 15:12:38 +00:00
Alex Bennée
899ba5edd8 tests/tcg/Makefile.target: fix path to config-host.mak
Since moving where the tests are run the path to config-host.mak has
been wrong. This doesn't affect much but things like the time fallback
for CONFIG_DEBUG_TCG and will also get in the way of checking for
PLUGINS support.

Fixes: fc76c56d3f
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-10-28 15:12:38 +00:00
Peter Maydell
786d36ad41 target-arm queue:
* Fix the CBAR register implementation for Cortex-A53,
    Cortex-A57, Cortex-A72
  * Fix direct booting of Linux kernels on emulated CPUs
    which have an AArch32 EL3 (incorrect NSACR settings
    meant they could not access the FPU)
  * semihosting cleanup: do more work at translate time
    and less work at runtime
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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190927' into staging

target-arm queue:
 * Fix the CBAR register implementation for Cortex-A53,
   Cortex-A57, Cortex-A72
 * Fix direct booting of Linux kernels on emulated CPUs
   which have an AArch32 EL3 (incorrect NSACR settings
   meant they could not access the FPU)
 * semihosting cleanup: do more work at translate time
   and less work at runtime

# gpg: Signature made Fri 27 Sep 2019 15:32:43 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190927:
  hw/arm/boot: Use the IEC binary prefix definitions
  hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots
  tests/tcg: add linux-user semihosting smoke test for ARM
  target/arm: remove run-time semihosting checks for linux-user
  target/arm: remove run time semihosting checks
  target/arm: handle A-profile semihosting at translate time
  target/arm: handle M-profile semihosting at translate time
  tests/tcg: clean-up some comments after the de-tangling
  target/arm: fix CBAR register for AArch64 CPUs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	tests/tcg/arm/Makefile.target
2019-09-30 11:02:22 +01:00
Alex Bennée
83704ceff1 tests/tcg: add linux-user semihosting smoke test for ARM
We already use semihosting for the system stuff so this is a simple
smoke test to ensure we are working OK on linux-user.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20190913151845.12582-7-alex.bennee@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-27 11:41:32 +01:00
Alex Bennée
72ab7f9e1d tests/tcg: clean-up some comments after the de-tangling
These were missed in the recent de-tangling so have been updated to be
more actuate. I've also built up ARM_TESTS in a manner similar to
AARCH64_TESTS for better consistency.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190913151845.12582-2-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-27 11:41:28 +01:00
Alex Bennée
b9fe0063b7 tests/tcg: add simple record/replay smoke test for aarch64
This adds two new tests that re-use the memory test to check basic
record replay functionality is still working. We have to define our
own runners rather than using the default pattern as we want to change
the test name but re-use the memory binary.

We declare the test binaries as PHONY as they don't really exist.

[AJB: A better test would output some sort of timer value or other
otherwise variable value so we could compare the record and replay
outputs and ensure they match]

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Cc: Pavel Dovgalyuk <dovgaluk@ispras.ru>
2019-09-26 19:00:53 +01:00
Alex Bennée
b059a62bb6 tests/tcg: add generic version of float_convs
This is broadly similar to the existing fcvt test for ARM but using
the generic float testing framework. We should be able to pare down
the ARM fcvt test case to purely half-precision with or without the
Alt HP provision.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26 19:00:53 +01:00
Alex Bennée
a4f3ed629e tests/tcg: add float_madds test to multiarch
This is a generic floating point multiply and accumulate test for
single precision floating point values. I've split of the common float
functions into a helper library so additional tests can use the same
common code.

As I don't have references for all architectures I've allowed some
flexibility for tests to pass without reference files. They can be
added as we get collect them.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26 19:00:53 +01:00
Alex Bennée
149911cff7 tests/tcg: re-enable linux-test for ppc64abi32
Now we have fixed the signal delivary bug we can remove this horrible
hack from the system.

Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26 19:00:53 +01:00
Alex Bennée
9a297fac5f tests/tcg: clean-up some comments after the de-tangling
These were missed in the recent de-tangling so have been updated to be
more actuate. I've also built up ARM_TESTS in a manner similar to
AARCH64_TESTS for better consistency.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-26 19:00:53 +01:00
David Hildenbrand
5d69cbdfdd tests/tcg: target/s390x: Test MVC
Let's add a test that especially verifies that no data will be touched
in case we cross page boundaries and one page access triggers a fault.

Before the fault-safe handling fixes, the test failes with:
      TEST    mvc on s390x
    data modified during a fault
    make[2]: *** [../Makefile.target:116: run-mvc] Error 1

Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-09-23 09:28:29 +02:00
David Hildenbrand
d9e13c3419 tests/tcg: target/s390x: Test MVO
Let's add the simple test based on the example from the PoP.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-09-23 09:28:29 +02:00
Alex Bennée
18b6be4326 tests/docker: move our arm64 cross compile to Buster
Now Buster is released we can unify our cross build images for both
QEMU and tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-10 14:14:31 +01:00
Alex Bennée
8cf4efcf30 tests/tcg: add .gitignore for in source builds
This hides the new build artefacts from the re-organised TCG tests when
you are doing an in-source build.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-10 14:14:31 +01:00
Paolo Bonzini
2038f8c877 tests/tcg: move configuration to a sub-shell script
Avoid the repeated inclusions of config-target.mak, which have
risks of namespace pollution, and instead build minimal configuration
files in a configuration script.  The same configuration files can
also be included in Makefile and Makefile.qemu

[AJB 10/09/19]
In the original PR this had inadvertently enabled tests
for ppc64abi32. However as the rest of the multiarch tests work rather
than disabling the otherwise correctly functioning build I've just
skipped the failing linux-test test. For some reason I can't debug it
with TCG so I'm leaving that to the PPC maintainers to look at.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20190807143523.15917-4-pbonzini@redhat.com>
[AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Richard Henderson <rth@twiddle.net>
2019-09-10 14:09:00 +01:00
Paolo Bonzini
fc76c56d3f tests/tcg: cleanup Makefile inclusions
Rename Makefile.probe to Makefile.prereqs and make it actually
define rules for the tests.

Rename Makefile to Makefile.target, since it is not a toplevel
makefile.

Rename Makefile.include to Makefile.qemu and disentangle it
from the QEMU Makefile.target, so that it is invoked recursively
by tests/Makefile.include.  Tests are now placed in
tests/tcg/$(TARGET).

Drop the usage of TARGET_BASE_ARCH, which is ignored by everything except
x86_64 and aarch64.  Fix x86 tests by using -cpu max and, while
at it, standardize on QEMU_OPTS for aarch64 tests too.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20190807143523.15917-3-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-10 09:38:33 +01:00
Paolo Bonzini
6a9e0ef32a tests/tcg: use EXTRA_CFLAGS everywhere
For i386 specifically, this allows using the host GCC
to compile the i386 tests.  But, it should really be
done for all targets, unless we want to pass $(EXTRA_CFLAGS)
directly as part of $(CC).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20190807143523.15917-2-pbonzini@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-10 09:38:33 +01:00
Alex Bennée
71ebbe09e9 tests/docker: fix "cc" command to work with podman
Podman requires a little bit of additional magic to the uid mapping
which was already done for the normal RunCommand. We simplify the
logic by pushing it directly into the Docker::run method to avoid
instantiating an extra Docker() object and ensure the CC command
always runs as the current user.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-09-10 09:38:33 +01:00
Aleksandar Markovic
6eed53f71b target/mips: tests/tcg: Fix target configurations for MSA tests
At this moment, the only MIPS CPUs that are emulated in QEMU and
support MSA extension are R5600 (mips32r5), and I6400/I6500 (mips64r6).
Therefore, mips32r5 and mips64r6 are the only ISAs that could support
MSA in QEMU. This means mips32r6 currently do not make much sense, and
mips32r5 support for MSA tests is needed, which is done by this patch.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1566216496-17375-38-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19 19:53:37 +02:00
Aleksandar Markovic
d7059fd737 target/mips: tests/tcg: Add optional printing of more detailed failure info
There is a need for printing input and output data for failure cases,
for debugging purpose. This is achieved by this patch, and only if a
preprocessor constant is manually set to 1. (Assumption is that the
need for such printout is relatively rare.)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1566216496-17375-37-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-19 19:53:37 +02:00
Alex Bennée
ef860047b6 tests/tcg: fix diff-out pass to properly report failure
A side effect of piping the output to head is squash the exit status
of the diff command. Fix this by only doing the pipe if the diff
failed and then ensuring the status is non-zero.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-07-10 10:31:22 +01:00
Alex Bennée
bd2c0f67e1 tests/tcg: fix up test-i386-fprem.ref generation
We never shipped the reference data in the source tree because it's
quite big (64M). As a result the only option is to generate it
locally. Although we have a rule to generate the reference file we
missed the dependency and location changes, probably because it's only
run for SLOW test runs.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-07-10 10:31:20 +01:00
Aleksandar Markovic
89a09189e0 tcg/tests: target/mips: Correct MSA test compilation and execution order
Correct MSA test compilation and execution order, for the sake of
consistence.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1562068213-11307-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02 14:20:24 +02:00
Aleksandar Markovic
391f77aaba tcg/tests: target/mips: Amend MSA integer multiply tests
Amend MSA fixed point multiply tests: correct output values for
MADDV.B, MADDV.H, MADDV.W, MADDV.D, MSUBV.B, MSUBV.H, MSUBV.W and
MSUBD.D.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1562068213-11307-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02 14:20:19 +02:00
Aleksandar Markovic
4cd013cd6e tcg/tests: target/mips: Amend MSA fixed point multiply tests
Amend MSA fixed point multiply tests: add tests for MADD_Q.H, MADD_Q.W,
MADDR_Q.H, MADDR_Q.W, MSUB_Q.H, MSUB_Q.W, MSUBR_Q.H and MSUBR_Q.W.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1562068213-11307-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02 14:20:11 +02:00
Peter Maydell
d247c8e7f4 - cleanup/refactoring in the cpu feature code
- fix for a tcg test case
 - halt/clear support for vfio-ccw, and use a new helper
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190701' into staging

- cleanup/refactoring in the cpu feature code
- fix for a tcg test case
- halt/clear support for vfio-ccw, and use a new helper

# gpg: Signature made Mon 01 Jul 2019 12:08:41 BST
# gpg:                using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg:                issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg:                 aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg:                 aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20190701:
  s390x: add cpu feature/model files to KVM section
  vfio-ccw: support async command subregion
  vfio-ccw: use vfio_set_irq_signaling
  s390x/cpumodel: Prepend KDSA features with "KDSA"
  s390x/cpumodel: Rework CPU feature definition
  tests/tcg/s390x: Fix alignment of csst parameter list

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02 11:48:39 +01:00
Aleksandar Markovic
23dd244baf tests/tcg: target/mips: Fix some test cases for pack MSA instructions
Fix certian test cases for MSA pack instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:51 +02:00
Aleksandar Markovic
4c399d066c tests/tcg: target/mips: Add support for MSA MIPS32R6 testings
Add files for MSA MIPS32R6 target testings (copiling and running).

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:46 +02:00
Aleksandar Markovic
5258822fcc tests/tcg: target/mips: Add support for MSA big-endian target testings
Add files for MSA big-endian target testings (copiling and running).

Little-endian files are renamed and ammended too.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:41 +02:00
Aleksandar Markovic
0b1450cce8 tests/tcg: target/mips: Amend tests for MSA int multiply instructions
Amend tests for MSA int multiply instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:33 +02:00
Aleksandar Markovic
c0a19f7bf1 tests/tcg: target/mips: Amend tests for MSA int dot product instructions
Add tests for instructions whose result depends on the value in destination
register (prior to instruction execution).

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:28 +02:00
Aleksandar Markovic
3d9569b855 tests/tcg: target/mips: Add tests for MSA move instructions
Add tests for MSA move instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:22 +02:00
Aleksandar Markovic
666952ea7c tests/tcg: target/mips: Add tests for MSA bit move instructions
Add tests for MSA bit move instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561543629-20327-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-26 13:25:17 +02:00
Cornelia Huck
60853009be One fix for a tcg test case and two cleanups/refactorings of cpu feature
definitions.
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Merge tag 's390x-tcg-2019-06-21' into s390-next-staging

One fix for a tcg test case and two cleanups/refactorings of cpu feature
definitions.

# gpg: Signature made Fri 21 Jun 2019 03:37:37 PM CEST
# gpg:                using RSA key 1BD9CAAD735C4C3A460DFCCA4DDE10F700FF835A
# gpg:                issuer "david@redhat.com"
# gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full]
# gpg:                 aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full]

* tag 's390x-tcg-2019-06-21':
  s390x/cpumodel: Prepend KDSA features with "KDSA"
  s390x/cpumodel: Rework CPU feature definition
  tests/tcg/s390x: Fix alignment of csst parameter list

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-06-24 17:30:18 +02:00
Richard Henderson
62a31161ee tests/tcg/s390x: Fix alignment of csst parameter list
The parameter list given in general register 1 shall be aligned
on a quadword boundary.  This test currently succeeds or fails
depending on the compiler version used and the accidential layout
of the function's stack frame.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-21 15:26:53 +02:00
Aleksandar Markovic
f9fa196bd7 tests/tcg: target/mips: Amend tests for MSA pack instructions
Add tests for cases when destination register is the same as one
of source registers.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561031359-6727-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21 11:30:36 +02:00
Aleksandar Markovic
8e6fe6b8ba tests/tcg: target/mips: Include isa/ase and group name in test output
For better appearance and usefullnes, include ISA/ASE name and
instruction group name in the output of tests. For example, all
this data will be displayed for FMAX_A.W test:

| MSA       | Float Max Min       | FMAX_A.W    |
| PASS:  80 | FAIL:   0 | elapsed time: 0.16 ms |

(the data will be displayed in one row; they are presented here in two
rows not to exceed the width of the commit message)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1561031359-6727-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21 11:30:31 +02:00
Richard Henderson
d67ebada15 target/arm: Fix output of PAuth Auth
The ARM pseudocode installs the error_code into the original
pointer, not the encrypted pointer.  The difference applies
within the 7 bits of pac data; the result should be the sign
extension of bit 55.

Add a testcase to that effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13 15:14:03 +01:00
Alex Bennée
db61edad7a tests/tcg/x86_64: add a PVH crt.o for x86_64 system tests
Instead of doing the full real to 64 bit dance we are attempting to
leverage Xen's PVH boot spec to go from 32 bit to 64 bit.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12 17:53:23 +01:00
Alex Bennée
2736b5cbee tests/tcg: clean-up VPATH/TESTS for i386
Since we only run build the multiarch tests and we use a fully
resolved path for the crt object we don't need the wildcard or VPATH
messing about.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12 17:53:22 +01:00
Alex Bennée
fcf112317c tests/tcg: better detect truncated reads
If we've truncated a wider read we can detect the condition earlier by
looking at the number of zeros we've read. So we don't trip up on
cases where we have written zeros to the start of the buffer we also
ensure we only start each offset read from the right address.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12 17:53:22 +01:00
Aleksandar Markovic
88e34ac062 tests/tcg: target/mips: Add README for MSA tests
Add README for MSA tests. This is just to explain how to run tests even
without Makefile. Makefile will be provided later on.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
8598f5fac1 tests/tcg: target/mips: Add tests for MSA FP max/min instructions
Add tests for MSA FP max/min instructions. This includes following
instructions:

  * FMAX.W - float maximum (words)
  * FMAX.D - float maximum (doublewords)
  * FMAX_A.W - float maximum absolute (words)
  * FMAX_A.D - float maximum absolute (doublewords)
  * FMIN.W - float minimum (words)
  * FMIN.D - float minimum (doublewords)
  * FMIN_A.W - float minimum absolute (words)
  * FMIN_A.D - float minimum absolute (doublewords)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
ca693d1c92 tests/tcg: target/mips: Add utility function reset_msa_registers()
Add function reset_msa_registers() and utilize it in each MSA test.
This is needed to ensure independency of test results on the state of
MSA registers before test execution. This also allows for correction
of tests for VSHF* instructions, that are now independent on the
previous state of MSA registers.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
b7c6798220 tests/tcg: target/mips: Move four tests to a better location
Move tests for <MUL|MULR>_Q.<H|B> from "integer multiply" directory
to "fixed-point multiply" directory, since they do not operate on
integers, but on fixed point numbers.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
99d423e576 tests/tcg: target/mips: Add tests for MSA shift instructions
Add tests for MSA shift instructions. This includes following
instructions:

  * SLL.B - shift left logical (bytes)
  * SLL.H - shift left logical (halfwords)
  * SLL.W - shift left logical (words)
  * SLL.D - shift left logical (doublewords)
  * SRA.B - shift right arithmetic (bytes)
  * SRA.H - shift right arithmetic (halfwords)
  * SRA.W - shift right arithmetic (words)
  * SRA.D - shift right arithmetic (doublewords)
  * SRAR.B - shift right arithmetic rounded (bytes)
  * SRAR.H - shift right arithmetic rounded (halfwords)
  * SRAR.W - shift right arithmetic rounded (words)
  * SRAR.D - shift right arithmetic rounded (doublewords)
  * SRL.B - shift right logical (bytes)
  * SRL.H - shift right logical (halfwords)
  * SRL.W - shift right logical (words)
  * SRL.D - shift right logical (doublewords)
  * SRLR.B - shift right logical rounded (bytes)
  * SRLR.H - shift right logical rounded (halfwords)
  * SRLR.W - shift right logical rounded (words)
  * SRLR.D - shift right logical rounded (doublewords)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
6ec12d4feb tests/tcg: target/mips: Amend and rearrange MSA wrappers
Amend and rearrange MSA wrappers to follow the same organization as
in MSA tests.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1559838440-9866-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07 11:53:07 +02:00
Aleksandar Markovic
1d336c87a3 tests/tcg: target/mips: Add tests for MSA bit set instructions
Add tests for MSA bit set instructions. This includes following
instructions:

  * BCLR.B - clear bit (bytes)
  * BCLR.H - clear bit (halfwords)
  * BCLR.W - clear bit (words)
  * BCLR.D - clear bit (doublewords)
  * BNEG.B - negate bit (bytes)
  * BNEG.H - negate bit (halfwords)
  * BNEG.W - negate bit (words)
  * BNEG.D - negate bit (doublewords)
  * BSET.B - set bit (bytes)
  * BSET.H - set bit (halfwords)
  * BSET.W - set bit (words)
  * BSET.D - set bit (doublewords)

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1555699081-24577-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01 20:20:20 +02:00
Aleksandar Markovic
750541c492 target/mips: Amend and cleanup MSA TCG tests
Add missing bits and peaces of the tests of the emulation of certain
MSA (non-immediate variants): some tests were missing two last cases;
some instructions were missing wrappers; some test included wrong
headers; some tests were missing altogether; updated some copywright
preambles; do several other minor cleanups.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1555699081-24577-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01 20:20:20 +02:00
David Gibson
c10aaaab0f tests: Fix up docker cross builds for ppc64 (BE) targets
We currently have docker cross building targets for powerpc (32-bit, BE)
and ppc64el (64-bit, LE), but not for pcp64 (64-bit, BE).  This is an
irritating gap in make check-tcg coverage so correct it.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-05-29 11:14:19 +10:00
Richard Henderson
8d8a8ab544 tests/tcg/alpha: add system boot.S
This provides the bootstrap and low level helper functions for an
alpha kernel.  We use direct access to the DP264 serial port for
test output, and hard machine halt to exit the emulation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20190501184306.15208-1-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
7ac283e963 tests/tcg/multiarch: expand system memory test to cover more
Expand the memory test to cover move of the softmmu code. Specifically
we:

  - improve commentary
  - add some helpers (for later BE support)
  - reduce boiler plate into helpers
  - add signed reads at various sizes/offsets
  - required -DCHECK_UNALIGNED

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
936647d3fc tests/tcg/minilib: support %c format char
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
67f3da9d74 tests/tcg/multiarch: move the system memory test
There is nothing inherently architecture specific about the memory
test although we may have to manage different restrictions of
unaligned access across architectures.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
f6482872f3 tests/tcg/aarch64: add system boot.S
This provides the bootstrap and low level helper functions for an
aarch64 kernel. We use semihosting to handle test output and exiting
the emulation. semihosting's parameter passing is a little funky so we
end up using the stack and pointing to that as the parameter block.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
49d755d02e tests/tcg/multiarch: add hello world system test
This is not really i386 only, we can have the same test for all
architectures supporting system tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Alex Bennée
8041650aef tests/tcg/multiarch: add support for multiarch system tests
We can certainly support some common tests for system emulation that
make use of our minimal defined boot.S support. It will still be up to
individual architectures to ensure they build so we provide a
MULTIARCH_TESTS variable that they can tack onto TESTS themselves.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28 10:28:51 +01:00
Max Filippov
b345e14053 target/xtensa: implement exclusive access option
The Exclusive Instructions provide a general-purpose mechanism for
atomic updates of memory-based synchronization variables that can be
used for exclusion algorithms.

Use cmpxchg-based implementation that is sufficient for the typical use
of exclusive access in atomic operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-05-15 10:31:52 -07:00
Max Filippov
bc19449acc tests/tcg/xtensa: clean up test set
Drop test_fail: we know that exit simcall works. Now that it's not run
automatically there's no point in keeping it.
Drop test_pipeline: we're not modeling pipeline, we don't control ccount
and there's no plan to do so.
Enable test_boolean: it won't break on cores without boolean option, it
will do testing on cores with boolean option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-23 14:42:05 -07:00
Max Filippov
b9ec52188f target/xtensa: fix break_dependency for repeated resources
break_dependency incorrectly handles the case of dependency on an opcode
that references the same register multiple times. E.g. the following
instruction is translated incorrectly:

  { or a2, a3, a3 ; or a3, a2, a2 }

This happens because resource indices of both dependency graph nodes are
incremented, and a copy for the second instance of the same register in
the ending node is not done.
Only increment resource index of the ending node of the dependency.
Add test.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-03-21 21:47:50 -07:00
Alex Bennée
b640728151 tests/tcg/arm: account for pauth randomness
Pointer authentication isn't guaranteed to always detect a clash
between different keys. Take this into account in the test by running
several times and checking the percentage hit rate of the test.

Cc: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
8a2af7a70c tests/tcg/i386: add memory test to exercise softmmu
This is a simple test to check various access patterns to memory
including unaligned access.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
40d6ee9450 tests/tcg/i386: add system mode Hello World test
This introduces the build framework for simple i386 system tests. The
first test is the eponymous "Hello World" which simply outputs the
text on the serial port and then exits.

I've included the framework for x86_64 but it is not in this series as
it is a work in progress.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
a113ec989b tests/tcg: provide a minilib for system tests
We will likely want a few common functions to make up for the fact we
don't have a libc and we don't want to feel like we are programming by
banging rocks together.

I've purloined the printf function from:

  https://git.virtualopensystems.com/dev/tcg_baremetal_tests

Although I have tweaked the names to avoid confusing GCC about clashing
with builtins.

Cc: Alexander Spyridakis <a.spyridakis@virtualopensystems.com>
Cc: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d72132c02e tests/tcg: enable cris base user-mode tests
This converts the existing Makefile into a Makefile.target and updates
it so it can be called by the tcg build system. The original Makefile
didn't set -cpu except for the v17 tests however that has broken (I
assume because linux-user is a "max" cpu) so here I force it to be
crisv17.

I've also replicated the GNU simulator targets (run-FOO-on-sim).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
f17365f518 tests/tcg/cris: align mul operations
To avoid:

  Error: dangerous MULS/MULU location; give it higher alignment

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
0056cb5790 tests/tcg/cris: comment out the ccs test
Evidently upstream gcc doesn't like this opcode.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d4f6e58fcb tests/tcg: split cris tests into bare and libc directories
Bare tests are standalone assembly tests that don't require linking to
any libc and hence can be built with kernel only compilers. The libc
tests need a compiler capable of building properly linked userspace
binaries. As we don't have such a cross compiler at the moment we
won't be building those tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
6b970dd62c tests/tcg/cris: cleanup sys.c
This is a mini library which provides helper functions to the tests
which are all currently written in assembly. A bunch of minor changes:

      - removed libc related headers (fedora-cris-cross is a system compiler)
      - re-organised the functions to avoid forward declarations
      - cleaned up brace usage
      - restored exit for _fail case
      - removed tabs and fixed indentation

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Stefan Hajnoczi
647aee9ba2 tests/tcg/arm: add ARMv6-M UNDEFINED 32-bit instruction test
Test that 32-bit instructions declared UNDEFINED in the ARMv6-M
Reference Manual really do raise an exception.  Also test that the 6
32-bit instructions defined in the ARMv6-M Reference Manual do not raise
an exception.

Based-on: <20181029194519.15628-1-stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20181129185113.30353-1-stefanha@redhat.com>
[AJB: integrated into system tests]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
be5cac175a tests/tcg/xtensa: enable system tests
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Philippe Mathieu-Daudé
c72d9df181 tests/docker: add debian-xtensa-cross image
Xtensa cpu supported:
- dc232b
- dc233c
- csp

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
b4f396151b tests/tcg/mips: fix hello-mips compilation
The compilation flags for proper building are in the source tree. We
also fix exit to 0 so the result is counted as a success.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
d0ce6257c6 tests/tcg: add gdb runner variant
With this you can launch a test in gdb with:

  cd $(BUILD)/tests
  make -f $(SRC)/tests/tcg/Makefile gdb-$(TEST_NAME)

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
fdfda70e28 tests/tcg: split run-test into user and system variants
We can't rely on shell redirect magic to get things right so lets
setup a common output chardev that is expecting to write to files. As
we have split run-test up we might as well move the default monitor
bits into the call.

Finally a little make sophistry is required to correctly quote
$(COMMA) and as we don't inherit common rules we have our own little
copy here.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
3d55c02624 tests/tcg: add QEMU_OPT option for test runner
This will allow tests to modify the QEMU invocation with for example
different -cpu stazas without having to define a whole new set of
runner types.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12 17:05:21 +00:00
Alex Bennée
bd15e6e004 tests/tcg: add softmmu awareness to Makefile
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-03-12 17:05:21 +00:00
Mateja Marjanovic
53e116fed6 target/mips: Add tests for a variety of MSA integer subtract instructions
Add tests for a variety of MSA integer subtract instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-6-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
4b302ce90d target/mips: Add tests for a variety of MSA integer multiply instructions
Add tests for a variety of MSA integer multiply instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-5-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
a8f91dd9fd target/mips: Add tests for a variety of MSA integer dot product instructions
Add tests for a variety of MSA integer dot product instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
72f463bc08 target/mips: Add tests for a variety of MSA integer divide instructions
Add tests for a variety of MSA integer divide instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Mateja Marjanovic
1be82d8901 target/mips: Add tests for a variety of MSA integer average instructions
Add tests for a variety of MSA integer average instructions.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551964929-17845-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-11 12:45:36 +01:00
Aleksandar Markovic
81526dff27 tests/tcg: target/mips: Rename two header files for consistency
Rename two header files for consistency and clarity. Do all other
changes to accommodate new names.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <amarkovic@wavecomp.com>
Message-Id: <1551981716-30664-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-11 12:36:58 +01:00
Aleksandar Markovic
dd8d6a2d5a tests/tcg: target/mips: Correct preambles of test source files
Correct preambles of test source files.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <amarkovic@wavecomp.com>
Message-Id: <1551981716-30664-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-11 12:36:49 +01:00
Mateja Marjanovic
0fdd986a6c target/mips: Add tests for integer add MSA instruction group
These are the regression tests for integer addition MSA instruction
- various flavors of instruction add (ADD, ADDS, HADD,...).

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1551718283-4487-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-05 17:05:33 +01:00
Aleksandar Markovic
2a367db039 tests/tcg: target/mips: Add tests for MSA pack instructions
Add tests for MSA pack instructions. This includes following
instructions:

  * PCKEV.B - pack even (bytes)
  * PCKEV.H - pack even (halfwords)
  * PCKEV.W - pack even (words)
  * PCKEV.D - pack even (doublewords)
  * PCKOD.B - pack odd (bytes)
  * PCKOD.H - pack odd (halfwords)
  * PCKOD.W - pack odd (words)
  * PCKOD.D - pack odd (doublewords)
  * VSHF.B - data preserving shuffle (bytes)
  * VSHF.H - data preserving shuffle (halfwords)
  * VSHF.W - data preserving shuffle (words)
  * VSHF.D - data preserving shuffle (doublewords)

Each test consists of 80 test cases, so altogether there are 960
test cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:44 +01:00
Aleksandar Markovic
7ecdacc568 tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructions
Add tests for MIPS64R6 integer multiply instructions: MUL, MUH, MULU,
MUHU, DMUL, DMUH, DMULU, and DMUHU.

MUH and MUHU require 64 bit inputs in the form of 64-bit sign-extended
32-bit inputs.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-14-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:33 +01:00
Aleksandar Markovic
09a1bc758e tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions
Add tests for MIPS64R6 shift instructions: SLLV, SRLV, SRAV, DSLLV,
DSRLV, and DSRAV.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:24 +01:00
Aleksandar Markovic
9dea2df848 tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions
Add tests for MIPS64R6 bit count instructions: CLO, CLZ, DCLO, and DCLZ.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-12-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:15 +01:00
Aleksandar Markovic
8708c32a47 tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions
Add tests for MIPS64R6 bit swap instructions: BITSWAP and DBITSWAP.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:03:04 +01:00
Aleksandar Markovic
99d46107f7 tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions
Add tests for MIPS64R6 logic instructions: AND, NOR, OR, and XOR.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:54 +01:00
Aleksandar Markovic
50dccc057f tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions
Add wrappers for some MIPS64R6 instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:46 +01:00
Aleksandar Markovic
6ae2e3bb33 tests/tcg: target/mips: Extend functionality of MSA wrapper macros
Add macros that will allow testing cases when one of the source
registers is identical to the destination register.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:37 +01:00
Aleksandar Markovic
dd3ba7036f tests/tcg: target/mips: Fix test utilities for 128-bit tests
Add "static" and "const" modifiers where appropriate, and fix other
minor issues.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:30 +01:00
Aleksandar Markovic
ace4458466 tests/tcg: target/mips: Add test utilities for 64-bit tests
Add test utilities for 64-bit tests. Some of MIPS64R6 instructions
require 64-bit inputs to be 32-bit integers sign-extedned to 64 bits,
hence the need for sets of such inputs.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:22 +01:00
Aleksandar Markovic
26b3256392 tests/tcg: target/mips: Add test utilities for 32-bit tests
Add test utilities for 32-bit tests.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:13 +01:00
Aleksandar Markovic
9e9509421f tests/tcg: target/mips: Add wrappers for various MSA instructions
Add wrappers for various MSA integer instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551800076-8104-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05 17:02:03 +01:00
Peter Maydell
4179575898 target/xtensa: FLIX support, various fixes and test improvements
- add FLIX (flexible length instructions extension) support;
 - make testsuite runnable on wider range of xtensa cores;
 - add floating point opcode tests;
 - don't add duplicate 'static' in import_core.sh script;
 - fix undefined opcodes detection in test_mmuhifi_c3 overlay.
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Merge remote-tracking branch 'remotes/xtensa/tags/20190228-xtensa' into staging

target/xtensa: FLIX support, various fixes and test improvements

- add FLIX (flexible length instructions extension) support;
- make testsuite runnable on wider range of xtensa cores;
- add floating point opcode tests;
- don't add duplicate 'static' in import_core.sh script;
- fix undefined opcodes detection in test_mmuhifi_c3 overlay.

# gpg: Signature made Thu 28 Feb 2019 12:53:23 GMT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190228-xtensa: (40 commits)
  tests/tcg/xtensa: add FPU2000 coprocessor tests
  tests/tcg/xtensa: add FP1 group tests
  tests/tcg/xtensa: add FP0 group conversion tests
  tests/tcg/xtensa: add FP0 group arithmetic tests
  tests/tcg/xtensa: add LSCI/LSCX group tests
  tests/tcg/xtensa: add test for FLIX
  tests/tcg/xtensa: conditionalize MMU-related tests
  tests/tcg/xtensa: conditionalize windowed register tests
  tests/tcg/xtensa: conditionalize and fix s32c1i tests
  tests/tcg/xtensa: fix SR tests for big endian configs
  tests/tcg/xtensa: conditionalize and expand SR tests
  tests/tcg/xtensa: conditionalize timer/CCOUNT tests
  tests/tcg/xtensa: conditionalize interrupt tests
  tests/tcg/xtensa: add straightforward conditionals
  tests/tcg/xtensa: conditionalize cache option tests
  tests/tcg/xtensa: conditionalize debug option tests
  tests/tcg/xtensa: enable boolean tests
  tests/tcg/xtensa: fix endianness issues in test_b
  tests/tcg/xtensa: don't use optional opcodes in generic code
  tests/tcg/xtensa: support configs with LITBASE
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-28 19:04:16 +00:00
Max Filippov
de0cebd930 tests/tcg/xtensa: add FPU2000 coprocessor tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:24 -08:00
Max Filippov
fd78bc55a4 tests/tcg/xtensa: add FP1 group tests
Test comparisons and conditional move operations.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:24 -08:00
Max Filippov
710b15f041 tests/tcg/xtensa: add FP0 group conversion tests
Test conversions for normal, NaN and Inf arguments.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9d012e8ec2 tests/tcg/xtensa: add FP0 group arithmetic tests
Test arithmetic operations for normal, NaN and Inf arguments.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
5e33b037b5 tests/tcg/xtensa: add LSCI/LSCX group tests
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
ebbd775aab tests/tcg/xtensa: add test for FLIX
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
3db8a95e70 tests/tcg/xtensa: conditionalize MMU-related tests
Make MMU-related tests conditional on the presence of MMUv2 option.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
c20e10eac8 tests/tcg/xtensa: conditionalize windowed register tests
Make windowed register tests conditional on the presence of this option.
Fix tests to work correctly for both 32 and 64 physical registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
00988da486 tests/tcg/xtensa: conditionalize and fix s32c1i tests
Make s32c1i tests conditional on the presence of this option. Initialize
ATOMCTL SR when it's present to allow RCW transactions on uncached
memory.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9b2d08a066 tests/tcg/xtensa: fix SR tests for big endian configs
SR tests generate instructions that the assembler does not recognize and
thus must take care about configuration endianness.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
50d3a0feae tests/tcg/xtensa: conditionalize and expand SR tests
Make tests for specific special registers conditional on the presence of
the options that add these registers and test that the registers are not
accessible otherwise.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
02a5a4a877 tests/tcg/xtensa: conditionalize timer/CCOUNT tests
Make timer/CCOUNT tests conditional on the presence of timer option and
number of configured timers. Don't use hard coded interrupt levels for
timers, use configured values.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
9c98822619 tests/tcg/xtensa: conditionalize interrupt tests
Make interrupt tests conditional on the presence of interrupt option and
on the presence of level-1 and high level software interrupts. Don't use
hard-coded interrupt level for the high level interrupt tests, choose
high level software IRQ and use its configured level.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
50f0171a95 tests/tcg/xtensa: add straightforward conditionals
Make tests for optional instruction groups conditional on the presence
of corresponding options in the config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
ecf5b57759 tests/tcg/xtensa: conditionalize cache option tests
Make data/instruction tests conditional on the presence of
data/instruction cache, whether they're lockable and whether data cache
is writeback.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
66c58ba71b tests/tcg/xtensa: conditionalize debug option tests
Make debug tests conditional on the presence of the debug option in the
config and tests that depend on the presence/number of instruction or
data breakpoint registers on the corresponding definitions. Use
configured debug interrupt level instead of the hardcoded value to set
up IRQ handler and access debug EPC register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
912f161ff7 tests/tcg/xtensa: enable boolean tests
Uncomment test_boolean in the test makefile. Make actual tests code
conditional on the presence of boolean option in the config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:23 -08:00
Max Filippov
64eef9bf95 tests/tcg/xtensa: fix endianness issues in test_b
Use bbci.l/bbsi.l instead of bbci/bbsi, as they are assembly macros that
accept little-endian bit number and produce correct immediate for both
little and big endian configurations. Choose value loaded into register
for bbc/bbs opcodes based on configuration endianness.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
fafd553343 tests/tcg/xtensa: don't use optional opcodes in generic code
Don't use 'loop' opcode in generic testsuite completion code, only use
core opcodes to make it work with any configuration.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
306a69dad4 tests/tcg/xtensa: support configs with LITBASE
Configurations with LITBASE register may use absolute literals by
default. Pass --no-absolute-literals option to assembler to use
PC-relative literals instead.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
906da88291 tests/tcg/xtensa: support configurations w/o vecbase
Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sections by assigning next offset to dot, as it may sometimes move dot
backwards and sometimes they may even belong to different memory region.
Don't group vectors into single output section. Instead put each vector
into its own section ant put it at its default virtual address.
Reserve 4KBytes from the default vectors base and put rest of the code
and data starting from there. Mark vectors sections as executable,
otherwise their contents is discarded. There may be as little as 16
bytes reserved for some vectors, load handler address into a0 and use
ret.n to jump there to make vector code fit into this 16 byte space.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov
0ed040db36 tests/tcg/xtensa: indicate failed tests
When test suite with multiple tests fails it's not obvious which test
failed. Pring "failed" in every invocation of test_fail. Do printing
when DEBUG preprocessor macro is defined.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Aleksandar Markovic
1e6bea794c tests/tcg: target/mips: Add tests for MSA integer max/min instructions
Add tests for MSA integer max/min instructions. This includes
following instructions:

  * MAX_A.B - maximum of absolute of two signed values (bytes)
  * MAX_A.H - maximum of absolute of two signed values (halfwords)
  * MAX_A.W - maximum of absolute of two signed values (words)
  * MAX_A.D - maximum of absolute of two signed values (doublewords)
  * MIN_A.B - minimum of absolute of two signed values (bytes)
  * MIN_A.H - minimum of absolute of two signed values (halfwords)
  * MIN_A.W - minimum of absolute of two signed values (words)
  * MIN_A.D - minimum of absolute of two signed values (doublewords)
  * MAX_S.B - maximum of two signed values (bytes)
  * MAX_S.H - maximum of two signed values (halfwords)
  * MAX_S.W - maximum of two signed values (words)
  * MAX_S.D - maximum of two signed values (doublewords)
  * MIN_S.B - minimum of two signed values (bytes)
  * MIN_S.H - minimum of two signed values (halfwords)
  * MIN_S.W - minimum of two signed values (words)
  * MIN_S.D - minimum of two signed values (doublewords)
  * MAX_U.B - maximum of two unsigned values (bytes)
  * MAX_U.H - maximum of two unsigned values (halfwords)
  * MAX_U.W - maximum of two unsigned values (words)
  * MAX_U.D - maximum of two unsigned values (doublewords)
  * MIN_U.B - minimum of two unsigned values (bytes)
  * MIN_U.H - minimum of two unsigned values (halfwords)
  * MIN_U.W - minimum of two unsigned values (words)
  * MIN_U.D - minimum of two unsigned values (doublewords)

Each test consists of 80 test cases, so altogether there are 1920
test cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
1f3a111ecc tests/tcg: target/mips: Add wrappers for MSA integer max/min instructions
Add wrappers for MSA integer max/min instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
520e210c0a tests/tcg: target/mips: Add tests for MSA integer compare instructions
Add tests for MSA integer compare instructions. This includes
following instructions:

  * CEQ.B - integer compare equal (bytes)
  * CEQ.H - integer compare equal (halfwords)
  * CEQ.W - integer compare equal (words)
  * CEQ.D - integer compare equal (doublewords)
  * CLE_S.B - signed integer compare less or equal (bytes)
  * CLE_S.H - signed integer compare less or equal (halfwords)
  * CLE_S.W - signed integer compare less or equal (words)
  * CLE_S.D - signed integer compare less or equal (doublewords)
  * CLE_U.B - unsigned integer compare less or equal (bytes)
  * CLE_U.H - unsigned integer compare less or equal (halfwords)
  * CLE_U.W - unsigned integer compare less or equal (words)
  * CLE_U.D - unsigned integer compare less or equal (doublewords)
  * CLT_S.B - signed integer compare less or equal (bytes)
  * CLT_S.H - signed integer compare less or equal (halfwords)
  * CLT_S.W - signed integer compare less or equal (words)
  * CLT_S.D - signed integer compare less or equal (doublewords)
  * CLT_U.B - unsigned integer compare less or equal (bytes)
  * CLT_U.H - unsigned integer compare less or equal (halfwords)
  * CLT_U.W - unsigned integer compare less or equal (words)
  * CLT_U.D - unsigned integer compare less or equal (doublewords)

Each test consists of 80 test cases, so altogether there are 1600 test
cases.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551185735-17154-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27 14:26:14 +01:00
Aleksandar Markovic
a4719aa85e tests/tcg: target/mips: Add wrappers for MSA integer compare instructions
Add wrappers for MSA integer compare instructions.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
e7bbc9b1c2 tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count'
Change directory name 'bit-counting' to 'bit-count'. This is just for
cosmetic and consistency sake. This was the only subdirectory in MSA
test directory that uses ending 'ing'.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
1f69d17856 tests/tcg: target/mips: Correct path to headers in some test source files
Correct path to headers in tests/tcg/mips/user/ase/msa/bit-counting/*
source files.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21 19:36:47 +01:00
Aleksandar Markovic
ba63292445 tests/tcg: target/mips: Add tests for MSA logic instructions
Add tests for MSA logic instructions. This includes following
instructions:

  * AND.V - logical AND
  * NOR.V - logical NOR
  * OR.V - logical OR
  * XOR.V - logical XOR

Each test consists of 80 test cases, so altogether there are 320
test cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
db37850bb4 tests/tcg: target/mips: Add wrappers for MSA logic instructions
Add wrappers for MSA logic instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
fc76f48667 tests/tcg: target/mips: Add tests for MSA interleave instructions
Add tests for MSA interleave instructions. This includes following
instructions:

  * ILVEV.B - interleave even (bytes)
  * ILVEV.H - interleave even (halfwords)
  * ILVEV.W - interleave even (words)
  * ILVEV.D - interleave even (doublewords)
  * ILVOD.B - interleave odd (bytes)
  * ILVOD.H - interleave odd (halfwords)
  * ILVOD.W - interleave odd (words)
  * ILVOD.D - interleave odd (doublewords)
  * ILVL.B - interleave left (bytes)
  * ILVL.H - interleave left (halfwords)
  * ILVL.W - interleave left (words)
  * ILVL.D - interleave left (doublewords)
  * ILVR.B - interleave right (bytes)
  * ILVR.H - interleave right (halfwords)
  * ILVR.W - interleave right (words)
  * ILVR.D - interleave right (doublewords)

Each test consists of 80 test cases, so altogether there are 1280
test cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
afdc3c515a tests/tcg: target/mips: Add wrappers for MSA interleave instructions
Add wrappers for MSA interleave instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
b62592ab65 tests/tcg: target/mips: Add tests for MSA bit counting instructions
Add tests for MSA bit counting instructions. This includes following
instructions:

  * NLOC.B - number of leading ones (bytes)
  * NLOC.H - number of leading ones (halfwords)
  * NLOC.W - number of leading ones (words)
  * NLOC.D - number of leading ones (doublewords)
  * NLZC.B - number of leading zeros (bytes)
  * NLZC.H - number of leading zeros (halfwords)
  * NLZC.W - number of leading zeros (words)
  * NLZC.D - number of leading zeros (doublewords)
  * PCNT.B - population count / number of ones (bytes)
  * PCNT.H - population count / number of ones (halfwords)
  * PCNT.W - population count / number of ones (words)
  * PCNT.D - population count / number of ones (doublewords)

Each test consists of 80 test cases, so altogether there are 960 test
cases.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
85c2a39300 tests/tcg: target/mips: Add wrappers for MSA bit counting instructions
Add a header that contains wrappers around MSA instructions assembler
invocations. For now, only bit counting instructions (NLOC, NLZC, and
PCNT; each in four data format flavors) are supported.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
08857c882d tests/tcg: target/mips: Add a header with test utilities
Add a header that contains test utilities. For now, it contains
only a function for checking and printing test results for bit
counting and similar MSA instructions.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
d33f672861 tests/tcg: target/mips: Add a header with test inputs
The file tests/tcg/mips/include/test_inputs.h is planned to
contain various test inputs. For now, it contains 64 128-bit
pattern inputs (alternating groups od ones and zeroes) and
16 128-bit random inputs.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Aleksandar Markovic
51a0e80c6e tests/tcg: target/mips: Remove an unnecessary file
Remove a file that was added long time ago by mistake. The commit
that introduced this file was commit d70080c4 (from 2012).

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-02-14 17:47:37 +01:00
Alex Bennée
d6db2a1cdf docker: add debian-buster-arm64-cross
We can't build QEMU with this but we can use this image to build newer
arm64 testcases which need more up to date tools.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-08 17:32:35 +00:00
Richard Henderson
06bf3b153a tests/tcg/aarch64: Add pauth smoke test
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190201195404.30486-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-05 16:52:39 +00:00
Aleksandar Markovic
dcca150f83 tests: tcg: mips: Remove old directories
Remove old test directories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Aleksandar Markovic
5e0aa63b08 tests: tcg: mips: Add two new Makefiles
Add Makefiles for two new direcitories.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Aleksandar Markovic
073d9f2ce0 tests: tcg: mips: Move source files to new locations
MIPS TCG test will be organized by ISAs and ASEs in future.

Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24 17:48:33 +01:00
Paolo Bonzini
7d37435bd5 avoid TABs in files that only contain a few
Most files that have TABs only contain a handful of them.  Change
them to spaces so that we don't confuse people.

disas, standard-headers, linux-headers and libdecnumber are imported
from other projects and probably should be exempted from the check.
Outside those, after this patch the following files still contain both
8-space and TAB sequences at the beginning of the line.  Many of them
have a majority of TABs, or were initially committed with all tabs.

    bsd-user/i386/target_syscall.h
    bsd-user/x86_64/target_syscall.h
    crypto/aes.c
    hw/audio/fmopl.c
    hw/audio/fmopl.h
    hw/block/tc58128.c
    hw/display/cirrus_vga.c
    hw/display/xenfb.c
    hw/dma/etraxfs_dma.c
    hw/intc/sh_intc.c
    hw/misc/mst_fpga.c
    hw/net/pcnet.c
    hw/sh4/sh7750.c
    hw/timer/m48t59.c
    hw/timer/sh_timer.c
    include/crypto/aes.h
    include/disas/bfd.h
    include/hw/sh4/sh.h
    libdecnumber/decNumber.c
    linux-headers/asm-generic/unistd.h
    linux-headers/linux/kvm.h
    linux-user/alpha/target_syscall.h
    linux-user/arm/nwfpe/double_cpdo.c
    linux-user/arm/nwfpe/fpa11_cpdt.c
    linux-user/arm/nwfpe/fpa11_cprt.c
    linux-user/arm/nwfpe/fpa11.h
    linux-user/flat.h
    linux-user/flatload.c
    linux-user/i386/target_syscall.h
    linux-user/ppc/target_syscall.h
    linux-user/sparc/target_syscall.h
    linux-user/syscall.c
    linux-user/syscall_defs.h
    linux-user/x86_64/target_syscall.h
    slirp/cksum.c
    slirp/if.c
    slirp/ip.h
    slirp/ip_icmp.c
    slirp/ip_icmp.h
    slirp/ip_input.c
    slirp/ip_output.c
    slirp/mbuf.c
    slirp/misc.c
    slirp/sbuf.c
    slirp/socket.c
    slirp/socket.h
    slirp/tcp_input.c
    slirp/tcpip.h
    slirp/tcp_output.c
    slirp/tcp_subr.c
    slirp/tcp_timer.c
    slirp/tftp.c
    slirp/udp.c
    slirp/udp.h
    target/cris/cpu.h
    target/cris/mmu.c
    target/cris/op_helper.c
    target/sh4/helper.c
    target/sh4/op_helper.c
    target/sh4/translate.c
    tcg/sparc/tcg-target.inc.c
    tests/tcg/cris/check_addo.c
    tests/tcg/cris/check_moveq.c
    tests/tcg/cris/check_swap.c
    tests/tcg/multiarch/test-mmap.c
    ui/vnc-enc-hextile-template.h
    ui/vnc-enc-zywrle.h
    util/envlist.c
    util/readline.c

The following have only TABs:

    bsd-user/i386/target_signal.h
    bsd-user/sparc64/target_signal.h
    bsd-user/sparc64/target_syscall.h
    bsd-user/sparc/target_signal.h
    bsd-user/sparc/target_syscall.h
    bsd-user/x86_64/target_signal.h
    crypto/desrfb.c
    hw/audio/intel-hda-defs.h
    hw/core/uboot_image.h
    hw/sh4/sh7750_regnames.c
    hw/sh4/sh7750_regs.h
    include/hw/cris/etraxfs_dma.h
    linux-user/alpha/termbits.h
    linux-user/arm/nwfpe/fpopcode.h
    linux-user/arm/nwfpe/fpsr.h
    linux-user/arm/syscall_nr.h
    linux-user/arm/target_signal.h
    linux-user/cris/target_signal.h
    linux-user/i386/target_signal.h
    linux-user/linux_loop.h
    linux-user/m68k/target_signal.h
    linux-user/microblaze/target_signal.h
    linux-user/mips64/target_signal.h
    linux-user/mips/target_signal.h
    linux-user/mips/target_syscall.h
    linux-user/mips/termbits.h
    linux-user/ppc/target_signal.h
    linux-user/sh4/target_signal.h
    linux-user/sh4/termbits.h
    linux-user/sparc64/target_syscall.h
    linux-user/sparc/target_signal.h
    linux-user/x86_64/target_signal.h
    linux-user/x86_64/termbits.h
    pc-bios/optionrom/optionrom.h
    slirp/mbuf.h
    slirp/misc.h
    slirp/sbuf.h
    slirp/tcp.h
    slirp/tcp_timer.h
    slirp/tcp_var.h
    target/i386/svm.h
    target/sparc/asi.h
    target/xtensa/core-dc232b/xtensa-modules.inc.c
    target/xtensa/core-dc233c/xtensa-modules.inc.c
    target/xtensa/core-de212/core-isa.h
    target/xtensa/core-de212/xtensa-modules.inc.c
    target/xtensa/core-fsf/xtensa-modules.inc.c
    target/xtensa/core-sample_controller/core-isa.h
    target/xtensa/core-sample_controller/xtensa-modules.inc.c
    target/xtensa/core-test_kc705_be/core-isa.h
    target/xtensa/core-test_kc705_be/xtensa-modules.inc.c
    tests/tcg/cris/check_abs.c
    tests/tcg/cris/check_addc.c
    tests/tcg/cris/check_addcm.c
    tests/tcg/cris/check_addoq.c
    tests/tcg/cris/check_bound.c
    tests/tcg/cris/check_ftag.c
    tests/tcg/cris/check_int64.c
    tests/tcg/cris/check_lz.c
    tests/tcg/cris/check_openpf5.c
    tests/tcg/cris/check_sigalrm.c
    tests/tcg/cris/crisutils.h
    tests/tcg/cris/sys.c
    tests/tcg/i386/test-i386-ssse3.c
    ui/vgafont.h

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20181213223737.11793-3-pbonzini@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Eric Blake <eblake@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-11 15:46:56 +01:00
Paolo Bonzini
72e21db7ea remove space-tab sequences
There are not many, and they are all simple mistakes that ended up
being committed.  Remove them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20181213223737.11793-2-pbonzini@redhat.com>
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-11 15:46:55 +01:00
Fredrik Noring
19749a21d7 tests/tcg: mips: Test R5900 three-operand MADDU1
Test R5900 three-operand MADDU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
8e2e5e7dac tests/tcg: mips: Test R5900 three-operand MADDU
Test R5900 three-operand MADDU.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
84dc071236 tests/tcg: mips: Test R5900 three-operand MADD1
Test R5900 three-operand MADD1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
Fredrik Noring
50f299da62 tests/tcg: mips: Test R5900 three-operand MADD
Test R5900 three-operand MADD.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
fabrice.desclaux@cea.fr
82c48fb79d Fixes i386 xchgq test
As "xchg" reads and writes both operands, the "+m" is required to avoid
undefined behavior on -O2 compilation.

Signed-off-by: Fabrice Desclaux <fabrice.desclaux@cea.fr>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <03506cf0-a204-f619-8ee4-4990a5e69af5@cea.fr>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-11 18:41:25 +01:00
Laurent Vivier
1f442da51e tests/tcg/multiarch: fix 32bit linux-test on 64bit host
Fix:

  TEST    linux-test on i386
  .../tests/tcg/multiarch/linux-test.c:201: readdir

readdir() calls getdents64() to have the list of the entries in a
directory, and getdents64() can return 64bit d_off values (with ext4,
for instance) that will not fit in the 32bit d_off field of the
readdir() dirent structure.

To avoid that, use readdir64() to use a 64bit d_off field too.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-11-14 11:07:06 +00:00
Stefan Weil
e50a61219f tests: Fix typos in comments and help message (found by codespell)
Fix also a grammar issue.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20180713054755.23323-1-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26 17:17:32 +02:00
Cleber Rosa
8c9a895aaf tests/tcg/README: fix location for lm32 tests
Point to the right and obvious location for lm32 tests.

Signed-off-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20181004161852.11673-3-crosa@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-10-26 17:17:32 +02:00
Fredrik Noring
35eb9be6bb tests/tcg/mips: Add tests for R5900 DIVU1
Add a test for DIVU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
990aa328be tests/tcg/mips: Add tests for R5900 DIV1
Add a test for DIV1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
4d261a6a59 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1
Add a test for MTLO1 and MTHI1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
3303f017ad tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1
Add a test for MFLO1 and MFHI1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
bec4d66b24 tests/tcg/mips: Add tests for R5900 three-operand MULTU1
Add a test for MULTU1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
cb56125eea tests/tcg/mips: Add tests for R5900 three-operand MULT1
Add a test for MULT1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
667eded270 tests/tcg/mips: Add tests for R5900 three-operand MULTU
Add a test for MULTU.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Fredrik Noring
9d35580a57 tests/tcg/mips: Add tests for R5900 three-operand MULT
Add a test for MULT.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-24 15:20:31 +02:00
Peter Maydell
8ca19bd882 target/xtensa updates:
- fix gdbstub register counts;
 - add big-endian core test_kc705_be;
 - convert to do_transaction_failed and add test for failed memory
   transactions;
 - fix couple FPU2000 bugs;
 - fix s32c1i implementation;
 - clean up exception handlers generation in xtensa tests;
 - add support for semihosting console input through a chardev.
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Merge remote-tracking branch 'remotes/xtensa/tags/20180918-xtensa' into staging

target/xtensa updates:

- fix gdbstub register counts;
- add big-endian core test_kc705_be;
- convert to do_transaction_failed and add test for failed memory
  transactions;
- fix couple FPU2000 bugs;
- fix s32c1i implementation;
- clean up exception handlers generation in xtensa tests;
- add support for semihosting console input through a chardev.

# gpg: Signature made Tue 18 Sep 2018 18:35:50 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <filippov@cadence.com>"
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>"
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20180918-xtensa:
  target/xtensa: support input from chardev console
  target/xtensa: fix s32c1i TCGMemOp flags
  tests/tcg/xtensa: only generate defined exception handlers
  tests/tcg/xtensa: move exception handlers to separate section
  target/xtensa: fix FPU2000 bugs
  tests/tcg/xtensa: add test for failed memory transactions
  target/xtensa: convert to do_transaction_failed
  target/xtensa: add test_kc705_be core
  target/xtensa: clean up gdbstub register handling
  target/xtensa: fix gdbstub register counts

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25 11:05:56 +01:00
Max Filippov
f68774ccd8 tests/tcg/xtensa: only generate defined exception handlers
Don't generate handlers for IRQ levels that are not defined for the CPU
or for window overflow/underflow exceptions for configs w/o windowed
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Max Filippov
f81aa02e0d tests/tcg/xtensa: move exception handlers to separate section
Not all CPU configurations may have enough space for handler code
between exception/interrupt vectors. Leave jumps to the handlers at the
vectors, but move all handlers past the vectors area.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Max Filippov
3ee01413be tests/tcg/xtensa: add test for failed memory transactions
Failed memory transactions should raise exceptions 14 (for fetch) or 15
(for load/store) with XEA2.

Memory accesses that result in TLB miss followed by an attempt to load
PTE from physical memory which fails should raise InstTLBMiss or
LoadStoreTLBMiss with XEA2.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Pavel Zbitskiy
3cea09271b target/s390x: fix PACK reading 1 byte less and writing 1 byte more
PACK fails on the test from the Principles of Operation: F1F2F3F4
becomes 0000234C instead of 0001234C due to an off-by-one error.
Furthermore, it overwrites one extra byte to the left of F1.

If len_dest is 0, then we only want to flip the 1st byte and never loop
over the rest. Therefore, the loop condition should be > and not >=.

If len_src is 1, then we should flip the 1st byte and pack the 2nd.
Since len_src is already decremented before the loop, the first
condition should be >=, and not >.

Likewise for len_src == 2 and the second condition.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-7-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
ad8c851d2e target/s390x: add EX support for TRT and TRTR
Improves "b213c9f5: target/s390x: Implement TRTR" by introducing the
intermediate functions, which are compatible with dx_helper type.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-6-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
478d360cd9 target/s390x: fix IPM polluting irrelevant bits
Suppose psw.mask=0x0000000080000000, cc=2, r1=0 and we do "ipm 1".
This command must touch only bits 32-39, so the expected output
is r1=0x20000000. However, currently qemu yields r1=0x20008000,
because irrelevant parts of PSW leak into r1 during program mask
transfer.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-5-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
dc95b31dac target/s390x: fix CSST decoding and runtime alignment check
CSST is defined as:

    C(0xc802, CSST,    SSF,   CASS, la1, a2, 0, 0, csst, 0)

It means that the first parameter is handled by in1_la1().
in1_la1() fills addr1 field, and not in1.

Furthermore, when extract32() is used for the alignment check, the
third parameter should specify the number of trailing bits that must
be 0. For FC these numbers are:

    FC=0 (word, 4 bytes):        2
    FC=1 (double word, 8 bytes): 3
    FC=2 (quad word, 16 bytes):  4

For SC these numbers correspond to the size:

    SC=0: 0
    SC=1: 1
    SC=2: 2
    SC=3: 3
    SC=4: 4

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-4-pavel.zbitskiy@gmail.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Pavel Zbitskiy
276ba120ed tests/tcg: add a simple s390x test
Copied from alpha.

Signed-off-by: Pavel Zbitskiy <pavel.zbitskiy@gmail.com>
Message-Id: <20180821025104.19604-2-pavel.zbitskiy@gmail.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2018-08-28 17:37:01 +02:00
Alex Bennée
28cbb997d6 tests: add check_invalid_maps to test-mmap
This adds a test to make sure we fail properly for a 0 length mmap.
There are most likely other failure conditions we should also check.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Cc: umarcor <1783362@bugs.launchpad.net>
Message-Id: <20180730134321.19898-3-alex.bennee@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-07-31 09:57:25 +02:00
Alex Bennée
1a3bdc6111 tests/tcg: remove runcom test
The combination of being rather esoteric and needing to support mmap @
0 means this only ever worked under translation. It has now regressed
even further and is no longer useful. Kill it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2018-07-24 11:45:25 +01:00
Alex Bennée
1a7fab926b tests: add top-level make dependency for docker builds
One problem with satisfying your docker dependencies in a sub-make it
you might end up trying to satisfy the dependency multiple times. This
is especially a problem with debian-sid based cross compilers and CI
setups. We solve this by doing a docker build pass at the top level
before any sub-makes are called.

We still need to satisfy dependencies in the Makefile.target call so
people can run tests from individual target directories. We introduce
a new Makefile.probe which gets called for each PROBE_TARGET and
allows us to build up the list. It does require multiply including
config-target.mak which shouldn't cause any issues as it shouldn't
define anything that clashes with config-host.mak. However we undefine
a few key variables each time around.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 22:13:32 +01:00
Alex Bennée
ab93256144 tests/tcg/i386: extend timeout for runcom test
The Travis hardware can be a little slow and the runcom test is fairly
heavy in calculating pi. Lets double the timeout so we don't trip up
during CI by mistake.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
83749e649e tests/tcg: override runners for broken tests
To get a clean run of check-tcg these tests are currently skipped:

  - hello-mips for mips
  - linux-test for sparc

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
607bf9b5a5 tests/tcg: add run, diff, and skip helper macros
As we aren't using the default runners for all the test cases it is
easy to miss out things like timeouts. To help with this we add some
helpers and use them so we only need to make core changes in one
place.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
c722a9e492 Makefile.target: add (clean-/build-)guest-tests targets
Now all the build infrastructure is in place we can build tests for
each guest that we support. That support mainly depends on having
cross compilers installed or docker setup. To keep all the logic for
that together we put the rules in tests/tcg/Makefile.include and
include it from the main Makefile.target.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
7e97017e7d tests/tcg/Makefile: update to be called from Makefile.target
This make is now invoked from each individual target make with the
appropriate CC and EXTRA_CFLAGS set for each guest. It then includes
additional Makefile.targets from:

  - tests/tcg/multiarch (always)
  - tests/tcg/$(TARGET_BASE_ARCH) (if available)
  - tests/tcg/$(TARGET_NAME)

The order is important as the later Makefile's may want to suppress
TESTS from its base arch profile. Each included Makefile.target is
responsible for adding TESTS as well as defining any special build
instructions for individual tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
97103c256e tests/tcg: enable building for PowerPC
Now we have restored debian-image-powerpc-cross using Debian SID
compilers we can build for 32 bit powerpc. Although PPC32 supports a
range of pages sizes currently only 4k works so the others are
commented out for now.

We can also merge the ppc64 support under the base architecture
directory to avoid too much proliferation of directories.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
e100a96755 tests/tcg: enable building for RISCV64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
33b2c4b50f tests/tcg: enable building for mips64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
cc6c7365b8 tests/tcg: enable building for sparc64
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
a5ec3e36dc tests/tcg: enable building for sh4
As before, using Debian SID compilers. While the compiler can be
coerced into generating big-endian code it seems the linker can't deal
with it so we only enable the building for little endian SH4.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
21d71c8c41 tests/tcg: enable building for m68k
As before, using Debian SID compilers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
3ae8a1000b tests/tcg: enable building for HPPA
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
4f2cbcfb4d tests/tcg/alpha: add Alpha specific tests
These tests did use their own crt.o stub however that is a little
stone age so we drop crt.S and just statically link to the cross
compilers libraries.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
409c1c9cbd tests/tcg: enable building for Alpha
We can't use our normal Debian based compilers as Alpha isn't an
officially supported architecture. However it is available as a port
and fortunately cross compilers for all these targets are included in
Debian Sid, the perpetual rolling/unstable/testing version of Debian.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
1e2107092d tests/tcg: enable building for ppc64
Currently this just enables building the multiarch tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
78353f49d2 tests/tcg: enable building for s390x
This doesn't add any additional tests but enables building the
multiarch tests for s390x.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: David Hildenbrand <david@redhat.com>
2018-06-20 20:22:34 +01:00
Alex Bennée
2ac93f19b6 tests/tcg/mips: include common mips hello-mips
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
7086ffbb93 tests/tcg: enable building for MIPS
This doesn't add any additional tests but enables building the
multiarch tests for MIPS using docker cross compilers. We don't have a
cross compiler for mips64 big endian though.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
106ea2db12 tests/tcg: move MIPS specific tests into subdir
These only need to be built for MIPS guests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
8ec8a55e3f tests/tcg/arm: add fcvt test cases for AArch32/64
This runs through the usual float to float conversions and crucially
also runs with ARM Alternative Half Precision Format.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
29e0436e3d tests/tcg: enable building for AArch64
We only have compilers for the (default) little endian variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
65eab0f8cb tests/tcg/arm: fix up test-arm-iwmmxt test
We need to rename the source file to a .S so we can do a single-line
assemble and link invocation. We also specify the additional CFLAGS
for the compile as it's a non-standard ARM binary.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[rth: force fpu configuration]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-20 20:22:34 +01:00
Alex Bennée
ab4aac5023 tests/tcg: enable building for ARM
This allows us to use the docker cross compiler image to build these
tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20 20:22:34 +01:00