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361 Commits

Author SHA1 Message Date
aurel32
d1258698f5 Add vsel and vperm instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:11:49 +00:00
aurel32
b04ae9811a Add vmsum{u,m}bm instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:11:39 +00:00
aurel32
707cec33f0 Add GEN_VAFORM_PAIRED macro for subsequent instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6178 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:11:29 +00:00
aurel32
6cf1c6e547 Add vupk{h,l}s{b,h} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:11:20 +00:00
aurel32
79f85c3ae9 Add vupk{h,l}px instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:11:10 +00:00
aurel32
de5f248499 Add GEN_VXFORM_NOA macro for subsequent instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6175 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:10:59 +00:00
aurel32
e4e6bee787 Add vsplt{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:10:49 +00:00
aurel32
27a4edb310 Add GEN_VXFORM_UIMM macro for subsequent instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6173 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:10:40 +00:00
aurel32
21d215831e Add GEN_VXFORM_SIMM macro for subsequent instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6172 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:10:28 +00:00
aurel32
cd633b10fd Add vsldoi instruction. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:10:09 +00:00
aurel32
5e1d0985f9 Add vrl{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:09:52 +00:00
aurel32
bf8d8ded57 Add lvs{l,r} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:09:42 +00:00
aurel32
e343da72b6 Add v{add,sub}cuw instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6168 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:09:31 +00:00
aurel32
7b239bec41 Add vs{l,r}o instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6167 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:09:19 +00:00
aurel32
d79f08096c Add vsl{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6166 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:09:08 +00:00
aurel32
07ef34c35e Add vsr{,a}{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6165 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:08:58 +00:00
aurel32
2c2779080c Add vmul{e,o}{s,u}{b,h} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:08:48 +00:00
aurel32
3b43004804 Add vmrg{l,h}{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:08:38 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate 
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:05:52 +00:00
aurel32
e40393399a Add v{min, max}{s, u}{b, h, w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6157 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 13:31:58 +00:00
aurel32
fab3cbe901 Add vavg{s,u}{b,h,w} instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6156 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 13:31:49 +00:00
aurel32
7872c51c1a Add v{add,sub}u{b,h,w}m instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6155 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 13:31:40 +00:00
aurel32
8e27dd6f09 Add GEN_VXFORM macro for subsequent instructions. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6154 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 13:31:30 +00:00
aurel32
e4704b3b11 Fix TCG error in gen_avr_ptr. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6152 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 13:31:10 +00:00
aurel32
501e23c4e8 target-ppc: fix TGC type mismatch introduced by r6146 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6147 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-03 12:35:38 +00:00
aurel32
df9247b264 tcg_temp_local_new should take no parameter 
This patch removes useless type information in some calls to
tcg_temp_local_new.  It also removes the parameter from the
macro declaration;  if a target has to use a specific non-default
size then it should use tcg_temp_local_new_{i32,i64}.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6146 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-01 14:09:05 +00:00
aurel32
564e571add target-ppc: add gen_avr_ptr function. 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6098 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-18 22:51:31 +00:00
aurel32
7a9b96cf21 target-ppc: add Altivec logical operations 
Use opc2/opc3 instead of one big xo field.  Do this consistency with the
rest of translate.c

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6087 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-18 22:42:58 +00:00
aurel32
eb44b959de target-ppc: update nip before calling an helper in FP instructions 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6045 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-15 17:13:39 +00:00
aurel32
330c483bbf target-ppc: fix TCGv type in fcmpu/fcmpo 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6044 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-15 17:13:31 +00:00
aurel32
9a819377d8 target-ppc: fix fcmp{o,u} instructions 
The instructions are specified to update the condition register even if
an error is to be signaled because of NaN input.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6034 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 19:34:09 +00:00
aurel32
b12363e1b7 target-ppc: remove FPRF optimization 
FPRF optimization is totally broken, remove it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6033 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 18:59:08 +00:00
aurel32
6e35d5243c target-ppc: fix mtfsb0 and mtfsb1 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6032 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 18:40:58 +00:00
aurel32
7889270acb target-ppc: display FPSCR in register dump 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6031 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 18:40:49 +00:00
aurel32
2637004698 target-ppc: fix mbar opcode 
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6027 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-14 11:12:20 +00:00
aurel32
a44d2ce18a target-ppc: fix compilation with CONFIG_SOFTFLOAT 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6003 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-13 11:46:27 +00:00
aurel32
e06fcd754e target-ppc: rework exception code 
... also remove two warnings.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-11 22:42:14 +00:00
aurel32
2a3ec4b5b3 target-ppc: remove dead code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5988 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-11 22:42:04 +00:00
aurel32
76db3ba44e target-ppc: memory load/store rework 
Rework the memory load/store:
- Unify load/store functions for 32-bit and 64-bit CPU
- Don't swap values twice for bit-reverse load/store functions
  in little endian mode.
- On a 64-bit CPU in 32-bit mode, do the address truncation for
  address computation instead of every load store. Truncate the
  address when incrementing the address (if needed)
- Cache writes to access_types.
- Add a few missing calls to gen_set_access_type()

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5949 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-08 18:11:21 +00:00
aurel32
0c34a5d722 target-ppc: kill a few warnings 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5941 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 23:00:00 +00:00
aurel32
e8fc4fa7a1 target-ppc: disable single stepping 
... which left was enabled by mistake.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5918 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 16:23:22 +00:00
aurel32
ec72e276c5 target-ppc: Fix use of uninitialized TCG variable in tlbiva 
Silences a warning about possible unitialized use of t0.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5915 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 15:45:15 +00:00
aurel32
45d827d2d7 target-ppc: convert SPR accesses to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 13:40:29 +00:00
aurel32
8983da70c4 target-ppc: remove dead code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5896 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-06 22:01:01 +00:00
aurel32
74d37793f4 target-ppc: convert SLB/TLB instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-06 21:46:17 +00:00
aurel32
06dca6a7c1 target-ppc: convert dcr load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-06 16:37:18 +00:00
aurel32
6527f6ea9c target-ppc: convert msr load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-06 13:03:35 +00:00
aurel32
22e0e17337 target-ppc: convert POWER bridge instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-06 12:19:14 +00:00
aurel32
7487953d70 target-ppc: convert POWER shift instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5882 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-05 07:21:44 +00:00
aurel32
54cdcae646 target-ppc: add functions to load/store SPR 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5881 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-05 07:21:31 +00:00
aurel32
ef0d51af1e target-ppc: convert PPC 440 instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 17:26:29 +00:00
aurel32
d72a19f7bd target-ppc: convert return from interrupt instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:55 +00:00
aurel32
fa407c030c target-ppc: convert external load/store instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5831 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:47 +00:00
aurel32
cf360a32af target-ppc: convert load/store with reservation instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5830 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:39 +00:00
aurel32
bdb4b68907 target-ppc: convert lscbx instruction to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:30 +00:00
aurel32
dfbc799d8e target-ppc: convert load/store string instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:21 +00:00
aurel32
37d269dfc6 target-ppc: convert icbi instruction to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:13 +00:00
aurel32
799a8c8d0a target-ppc: convert dcbz instruction to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:24:05 +00:00
aurel32
ff4a62cd81 target-ppc: convert load/store multiple instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:23:56 +00:00
aurel32
931ff27258 target-ppc: convert wait instruction to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5824 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:23:46 +00:00
aurel32
cf02a65c77 target-ppc: convert mfrom instruction to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5823 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:23:35 +00:00
aurel32
0f3955e2d2 target-ppc: convert software TLB instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5819 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:22:56 +00:00
aurel32
01a4afeb99 target-ppc: convert POWER2 load/store instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5805 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-27 19:30:56 +00:00
aurel32
6a6ae23f3c target-ppc: convert SPE load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5804 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-27 19:30:47 +00:00
aurel32
38d1495201 target-ppc: simplify evsplati and evsplatfi 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5803 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-27 19:30:38 +00:00
aliguori
c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka) 
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-25 22:13:57 +00:00
aurel32
cab3bee2d6 target-ppc: convert trap instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5788 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-24 11:28:19 +00:00
aurel32
fe1e5c53fd target-ppc: convert altivec load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5787 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-24 08:47:21 +00:00
aurel32
a0d7d5a776 target-ppc: convert FPU load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5786 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-23 16:30:50 +00:00
aurel32
a7859e892b target-ppc: fix access_type usage 
Write env->access_type before a load/store operation instead of relying
on the name of the dyngen operation.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5785 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-23 16:30:40 +00:00
aurel32
0c8aacd466 target-ppc: include the instruction name in load/store handlers name 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5784 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-23 16:30:28 +00:00
aurel32
1c97856dcc target-ppc: convert SPE FP ops to TCG 
Including a few bug fixes:
- Don't clear high part for instruction with 32-bit destination
- Fix efscmp* and etstcmp* return value

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5783 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-23 10:54:04 +00:00
aurel32
64adab3fcb target-ppc: convert exceptions generation to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5772 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-22 10:09:17 +00:00
aurel32
0f2f39c234 target-ppc: fix TCG type errors introduced in r5754 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5756 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-19 17:54:49 +00:00
aurel32
af12906f77 target-ppc: convert fp ops to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5754 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-19 16:10:23 +00:00
aliguori
a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka) 
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 20:07:32 +00:00
aurel32
87006d1378 target-ppc: fix regression introduced by commit 5729 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5733 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 09:32:01 +00:00
pbrook
a7812ae412 TCG variable type checking. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-17 14:43:54 +00:00
aurel32
57951c2742 target-ppc: convert most SPE integer instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5668 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-10 11:10:23 +00:00
aurel32
741a7444a3 target-ppc: fix TCG argument 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5661 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 18:27:28 +00:00
aurel32
a973001797 target-ppc: Remove a few TCG temp variable leaks 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5660 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 17:27:36 +00:00
aurel32
ec6469a3b1 target-ppc: fixes for gen_op_neg() 
- Rename to gen_op_arith_neg for consistency with other functions.
- Correctly free TCG temp variable.
- Fix the return value in 64-bit mode in case of overflow.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 17:27:27 +00:00
aurel32
2ef1b120d1 target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes 
gen_op_arith_divw():
- "deoptimize" gen_op_arith_divw to make it more readable.
- Correctly free TCG temp variable

gen_op_arith_divd():
- Call the right function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5658 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 17:27:19 +00:00
aurel32
1e4c090f7d target-ppc: optimize mullw and make the code more readable 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5657 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 17:27:11 +00:00
aurel32
bdc4e053d1 target-ppc: indentation fixes 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5656 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-09 17:27:03 +00:00
aurel32
4870167d04 target-ppc: fix tcg fatal error on i386 host 
It looks like the i386 runs out of registers for allocation due
to too many global registers allocated by the ppc target.

Here is a quick and dirty fix that seems to solve the problem.
This should be considered as temporary.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5648 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-08 08:57:45 +00:00
aurel32
e32ad5c268 target-ppc: fix flags computation for tcg_gen_qemu_st 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5644 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-07 13:48:25 +00:00
aurel32
54843a5861 target-ppc: use the new rotr/rotri instructions 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5608 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-03 07:08:44 +00:00
aurel32
fdce4963ea target-ppc: use the new subfi wrapper 
(...and fix rldnm)

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5600 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:23:14 +00:00
aurel32
0cfe58cd44 target-ppc: simplify slw, srw, sld, srd 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5597 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:22:45 +00:00
aurel32
fea0c503a0 target-ppc: be more consistent with temp variables naming 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5596 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:22:34 +00:00
aurel32
4da0033e6e target-ppc: fix srw on 64-bit targets 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5595 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-02 08:22:16 +00:00
aurel32
182608d44c target-ppc: convert 405 MAC instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5591 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-01 00:54:23 +00:00
aurel32
7463740644 target-ppc: convert arithmetic functions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5590 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-01 00:54:12 +00:00
aurel32
269f3e95e8 target-ppc: fix XER accesses on 64-bit targets 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5588 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-01 00:53:48 +00:00
aurel32
ea36369470 target-ppc: use consistent names for variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5557 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-27 22:50:39 +00:00
aurel32
312179c419 target-ppc: indentation fixes 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5556 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-27 22:50:31 +00:00
aurel32
d03ef5116b target-ppc: convert rotation instructions to TCG 
Also fix rlwimi and rldimi for corner cases.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5555 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-27 22:50:22 +00:00
pbrook
2e31f5d38c Fix typos in PPC TCG conversion. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5521 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-24 12:03:16 +00:00
aurel32
a2ffb81204 target-ppc: convert branch related instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5508 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 16:31:31 +00:00
aurel32
26d6736245 target-ppc: convert logical instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5506 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:31:27 +00:00
aurel32
e1571908a2 target-ppc: convert crf related instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5505 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:31:14 +00:00
aurel32
cf960816f9 target-ppc: use the new TCG logical operations 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5503 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:29:55 +00:00
aurel32
3d7b417e13 target-ppc: Convert XER accesses to TCG 
Define XER bits as a single register and access them individually to
avoid defining 5 32-bit registers (TCG doesn't permit to map 8-bit
registers).

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5500 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-21 11:28:46 +00:00
aurel32
ed69522caf PPC: fix dcbi instruction 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5495 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-15 22:25:21 +00:00
aurel32
3d3a6a0a48 PPC: convert SPE logical instructions to TCG 
(Nathan Froyd)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5494 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-15 17:00:45 +00:00
aurel32
b61f2753a7 ppc: convert integer load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5493 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-15 17:00:37 +00:00
aurel32
19f98ff634 target-ppc: fix a TCG local variable creation 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5492 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-15 17:00:29 +00:00
aurel32
f0aabd1aa3 PPC: convert SPE effective address computation to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-15 17:00:18 +00:00
aurel32
e2be8d8d7e PPC: convert effective address computation to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5490 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-14 19:55:54 +00:00
aurel32
ee600be6a6 ppc: fix crash in ppc system single step support 
There was a bogus case where two system debug ops get generated.  This
patch removes the broken system debug op. This was a left over after
making some changes to correctly generate debug ops on branch
operations inside gen_goto_tb();

The test case against this patch is to turn on single stepping with
timers, boot a linux kernel, set a breakpoint a do_fork and in gdb
execute "si 3000".  Then qemu-system-ppc will fault executing a debug
op, which should not have been executed.

Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5391 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-01 22:01:37 +00:00
pbrook
36aa55dcd9 Add concat_i32_i64 op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-21 13:48:32 +00:00
blueswir1
b55266b5a2 Suppress gcc 4.x -Wpointer-sign (included in -Wall) warnings 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-20 08:07:15 +00:00
aurel32
0df5bdbe0f ppc: Convert op_andi to TCG 
Replace op_andi_... with tcg_gen_andi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5218 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-14 18:30:32 +00:00
aurel32
cfdcd37aa5 ppc: Convert ctr, lr moves to TCG 
Introduce TCG variables cpu_{ctr,lr} and replace op_{load,store}_{lr,ctr}
with tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5217 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-14 18:30:23 +00:00
aurel32
7c417963f7 ppc: Convert op_subf to TCG 
Replace op_subf with tcg_gen_sub_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5168 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-05 14:19:51 +00:00
aurel32
39dd32eed2 ppc: Convert op_add, op_addi to TCG 
Replace op_add with tcg_gen_add_tl and op_addi with tcg_gen_addi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5167 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-05 14:19:43 +00:00
aurel32
489251fa54 ppc: replace op_set_FT0 with tcg_gen_movi_i64 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5162 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 20:34:31 +00:00
aurel32
bd568f1849 ppc: Convert nip moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5160 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 18:06:03 +00:00
aurel32
d38ff48941 ppc: remove unused code 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5159 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 17:16:41 +00:00
aurel32
47e4661cc4 ppc: Convert CRF moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5158 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 17:06:47 +00:00
aurel32
ec1ac72d9c ppc: fix fpr TCG registers creation 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5157 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 15:49:12 +00:00
aurel32
a5e26afa61 ppc: Convert FPR moves to TCG 
Replace op_{load,store}_fpr with tcg_gen_mov_i64.
Introduce i64 TCG variables cpu_fpr[0..31] and cpu_FT[0..2].

This obsoletes op_template.h for REG > 7.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5156 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 14:43:54 +00:00
aurel32
1d54269590 ppc: Convert Altivec register moves to TCG 
Replace op_{load,store}_avr with helpers gen_{load,store}_avr.
Introduce two sets of i64 TCG variables, cpu_avr{h,l}[0..31], and
cpu_AVR{h,l}[0..2].

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5155 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 14:43:45 +00:00
aurel32
bd7d9a6d7b ppc: cleanup register types 
- use target_ulong for gpr and dyngen registers
- remove ppc_gpr_t type
- define 64-bit dyngen registers for GPE register on 32-bit targets

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5154 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 05:26:09 +00:00
aurel32
f78fb44e82 ppc: Convert GPR moves to TCG 
Replace op_load_gpr_{T0,T1,T2} and op_store_{T0,T1,T2} with tcg_gen_mov_tl.
Introduce TCG variables cpu_gpr[0..31].

For the SPE extension, assure that ppc_gpr_t is only uint64_t for ppc64.
Introduce TCG variables cpu_gprh[0..31] for upper 32 bits on ppc and helpers
gen_{load,store}_gpr64. Based on suggestions by Aurelien, Thiemo and Blue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5153 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-04 05:25:47 +00:00
aurel32
f0413473ff [ppc] Convert op_moven_T2_T0 to TCG 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5143 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 23:26:40 +00:00
aurel32
86c581dc80 [ppc] Convert op_reset_T0, op_set_{T0, T1} to TCG 
Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5142 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 23:26:32 +00:00
aurel32
e55fd9340e [ppc] Convert op_move_{T1,T2}_T0 to TCG 
Attached patch replaces op_move_T1_T0 and op_move_T2_T0 with
tcg_gen_mov_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5137 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 16:19:05 +00:00
aurel32
02f4f6c24c [ppc] Convert gen_set_{T0,T1} to TCG 
The attached patch replaces gen_set_T0 and gen_set_T1 with
tcg_gen_movi_tl.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5136 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-02 16:18:55 +00:00
aurel32
f10dc08e00 PPC: add support for TCG helpers 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5094 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:01:45 +00:00
aurel32
1c73fe5bba PPC: Init TCG variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5093 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:01:36 +00:00
aurel32
6676f42453 Revert commits 5082 and 5083 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5084 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 23:16:35 +00:00
aurel32
61c0480722 PPC: Switch a few instructions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5083 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 19:05:35 +00:00
aurel32
c0692e3c65 PPC: Init TCG variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5082 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-24 19:05:26 +00:00
ths
9ceb2a77ad Fix encoding of efsctsiz (powerpc spe), by Tristan Gingold. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4999 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-13 11:30:10 +00:00
ths
2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 18:01:29 +00:00
pbrook
b2437bf267 Add missing static qualifiers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 12:29:56 +00:00
pbrook
2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00
aurel32
e4bb997e06 PPC: fix mtfsfi 
(Tristan Gingold)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4748 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-18 22:10:12 +00:00
ths
1235fc066a Spelling fixes, by Stefan Weil. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4655 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-03 19:51:57 +00:00
aurel32
8cbcb4fa2c Fix broken PPC user space single stepping 
(Jason Wessel)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-10 23:28:14 +00:00
aurel32
fd501a05c6 PPC: fix isel opcode decoding 
(Tristan Gingold)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4345 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-05 21:27:18 +00:00
aurel32
d2856f1ad4 Factorize code in translate.c 
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-28 00:32:32 +00:00
aurel32
ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
bellard
57fec1fee9 use the TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:50:11 +00:00
j_mayer
6b542af760 Fix incorrect debug prints (reported by Paul Brook). 
Remove obsolete / duplicated debug prints and improve output consistency.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3725 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-24 02:03:55 +00:00
j_mayer
e7c240035f Add new sane low-level memory accessors for PowerPC that do proper 
size or zero extension, with homogenous names.
Fix load & store strings: those are now endian-sensitive, by definition.
Fix dcbz: must always align the target address to a cache line boundary.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3719 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-22 11:00:46 +00:00
j_mayer
5b8105fa50 PowerPC instruction fixes: 
- hrfid is part of the hypervisor extension
- fix stfiwx naming


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3705 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-19 11:39:29 +00:00
j_mayer
c8623f2e37 Fix another collision in PowerPC instructions definitions. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3702 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-19 01:48:51 +00:00