38cb336fe9
9188 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Strahinja Jankovic
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22bd244a1c |
tests/avocado: Add SD boot test to Cubieboard
Cubieboard now can boot directly from SD card, without the need to pass `-kernel` parameter. Update Avocado tests to cover this functionality. Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20221226220303.14420-8-strahinja.p.jankovic@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Daniel P. Berrangé
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88a0ef00d7 |
enforce use of G_GNUC_PRINTF attributes
We've been very gradually adding G_GNUC_PRINTF annotations to functions over years. This has been useful in detecting certain malformed printf strings, or cases where we pass user data as the printf format which is a potential security flaw. Given the inherant memory corruption danger in use of format strings vs mis-matched variadic arguments, it is worth applying G_GNUC_PRINTF to all functions using printf, even if we know they are safe. The compilers can reasonably reliably identify such places with the -Wsuggest-attribute=format / -Wmissing-format-attribute flags. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20221219130205.687815-7-berrange@redhat.com> [-Wsuggest-attribute=format and -Wmissing-format-attribute are synonyms, only include one; disable it for testfloat. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Daniel P. Berrangé
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0472b2e541 |
tests: add G_GNUC_PRINTF for various functions
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20221219130205.687815-6-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Peter Maydell
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aa96ab7c9d |
* s390x header clean-ups from Philippe
* Rework and improvements of the EINTR handling by Nikita * Deprecate the -no-hpet command line option * Disable the qtests in the 32-bit Windows CI job again * Some other misc fixes here and there -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmO8It8RHHRodXRoQHJl ZGhhdC5jb20ACgkQLtnXdP5wLbUwbA//dXgfHy95C1r2nTMDekk09+KkmNB1f6M8 3HK4ROmmrMT/aP9FwfqMBT7JHM/m4bwOGw0Sula8vfjg9NYGPWuSYjdObWKnrIq/ YORoTxqak9c98Co06EQbAfWn3Pj0ifQkX+FIyzcNGhu4856FWdBsMuyq52VLi36q Z8ruSOmclzluoIB3mVYY/s5J7ED2A3K0h39frKLE9FGsKObX10KWj+MZyDHi9oGZ ucTHai12OXgNghjlrwI0BqJziih4NxfIWs0JovSo3cN0at7m57G5JChjR38zTMNT 2Q46tDKoIXesY1GUmVuIgJ5F1Uoshc8Pz5qBSQ5mUbZUQMpivhFrEB666wsYmPd1 M/YwnZ+PFhWjem7p28fKmnmkeATvE0S+vMDifTVZ880nmAbyUm1vFKfqV6r2mBrT p4iXfh/9easFfJWHueU4fBwyMndDGRaCRJnP8KQ5I9yb0WZbt+/0k/y8CQD8Oxr7 dNFFFoY3KnIO9DCRO5Wr+3OqUgtSAQyhBDf5V2wSMCFrwPHKsvWKSbdiWR3Qe4ck 41InWgawB3xx57+vXraDUA10+nBZ1VrM92ObqfLPTFqjLCom6Fm85cG4YFRLIvRt rdlOC+ScpeVpec7MwcHrScGL0HmUgPnShDAo07pRy4oKK+c89sXzdAFf2nYJTAWS WCuChrn7VFM= =D+Yw -----END PGP SIGNATURE----- Merge tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu into staging * s390x header clean-ups from Philippe * Rework and improvements of the EINTR handling by Nikita * Deprecate the -no-hpet command line option * Disable the qtests in the 32-bit Windows CI job again * Some other misc fixes here and there # gpg: Signature made Mon 09 Jan 2023 14:21:19 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-01-09' of https://gitlab.com/thuth/qemu: .gitlab-ci.d/windows: Do not run the qtests in the msys2-32bit job error handling: Use RETRY_ON_EINTR() macro where applicable Refactoring: refactor TFR() macro to RETRY_ON_EINTR() docs/interop: Change the vnc-ledstate-Pseudo-encoding doc into .rst i386: Deprecate the -no-hpet QEMU command line option tests/qtest/bios-tables-test: Replace -no-hpet with hpet=off machine parameter tests/readconfig: spice doesn't support unix socket on windows yet target/s390x: Restrict sysemu/reset.h to system emulation target/s390x/tcg/excp_helper: Restrict system headers to sysemu target/s390x/tcg/misc_helper: Remove unused "memory.h" include hw/s390x/pv: Restrict Protected Virtualization to sysemu exec/memory: Expose memory_region_access_valid() MAINTAINERS: Add MIPS-related docs and configs to the MIPS architecture section tests/vm: Update get_default_jobs() to work on non-x86_64 non-KVM hosts qemu-iotests/stream-under-throttle: do not shutdown QEMU Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Nikita Ivanov
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37b0b24e93 |
error handling: Use RETRY_ON_EINTR() macro where applicable
There is a defined RETRY_ON_EINTR() macro in qemu/osdep.h which handles the same while loop. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/415 Signed-off-by: Nikita Ivanov <nivanov@cloudlinux.com> Message-Id: <20221023090422.242617-3-nivanov@cloudlinux.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> [thuth: Dropped the hunk that changed socket_accept() in libqtest.c] Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Nikita Ivanov
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8b6aa69365 |
Refactoring: refactor TFR() macro to RETRY_ON_EINTR()
Rename macro name to more transparent one and refactor it to expression. Signed-off-by: Nikita Ivanov <nivanov@cloudlinux.com> Message-Id: <20221023090422.242617-2-nivanov@cloudlinux.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Schoenebeck <qemu_oss@crudebyte.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Thomas Huth
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9a2112f9ae |
tests/qtest/bios-tables-test: Replace -no-hpet with hpet=off machine parameter
We are going to deprecate (and finally remove later) the -no-hpet command line option. Prepare the bios-tables-test by using the replacement hpet=off machine parameter instead. Message-Id: <20230109081205.116369-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Marc-André Lureau
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beecc4b78d |
tests/readconfig: spice doesn't support unix socket on windows yet
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20230103110814.3726795-6-marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Philippe Mathieu-Daudé
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44c8a6ab45 |
tests/vm: Update get_default_jobs() to work on non-x86_64 non-KVM hosts
On non-x86_64 host, if KVM is not available we get:
Traceback (most recent call last):
File "tests/vm/basevm.py", line 634, in main
vm = vmcls(args, config=config)
File "tests/vm/basevm.py", line 104, in __init__
mem = max(4, args.jobs)
TypeError: '>' not supported between instances of 'NoneType' and 'int'
Fix by always returning a -- not ideal but safe -- '1' value.
Fixes:
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Christian Borntraeger
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ad302b21aa |
qemu-iotests/stream-under-throttle: do not shutdown QEMU
Without a kernel or boot disk a QEMU on s390 will exit (usually with a disabled wait state). This breaks the stream-under-throttle test case. Do not exit qemu if on s390. Signed-off-by: Christian Borntraeger <borntraeger@linux.ibm.com> Message-Id: <20221207131452.8455-1-borntraeger@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com> |
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Peter Maydell
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d6271b6572 |
virtio,pc,pci: features, cleanups, fixes
mostly vhost-vdpa:
guest announce feature emulation when using shadow virtqueue
support for configure interrupt
startup speed ups
an acpi change to only generate cluster node in PPTT when specified for arm
misc fixes, cleanups
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
-----BEGIN PGP SIGNATURE-----
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Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
virtio,pc,pci: features, cleanups, fixes
mostly vhost-vdpa:
guest announce feature emulation when using shadow virtqueue
support for configure interrupt
startup speed ups
an acpi change to only generate cluster node in PPTT when specified for arm
misc fixes, cleanups
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Sun 08 Jan 2023 08:01:39 GMT
# gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (50 commits)
vhost-scsi: fix memleak of vsc->inflight
acpi: cpuhp: fix guest-visible maximum access size to the legacy reg block
tests: acpi: aarch64: Add *.topology tables
tests: acpi: aarch64: Add topology test for aarch64
tests: acpi: Add and whitelist *.topology blobs
tests: virt: Update expected ACPI tables for virt test
hw/acpi/aml-build: Only generate cluster node in PPTT when specified
tests: virt: Allow changes to PPTT test table
virtio-pci: fix proxy->vector_irqfd leak in virtio_pci_set_guest_notifiers
vdpa: commit all host notifier MRs in a single MR transaction
vhost: configure all host notifiers in a single MR transaction
vhost: simplify vhost_dev_enable_notifiers
vdpa: harden the error path if get_iova_range failed
vdpa-dev: get iova range explicitly
docs/devel: Rules on #include in headers
include: Include headers where needed
include/hw/virtio: Break inclusion loop
include/hw/cxl: Break inclusion loop cxl_pci.h and cxl_cdat_h
include/hw/pci: Include hw/pci/pci.h where needed
include/hw/pci: Split pci_device.h off pci.h
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Peter Maydell
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3d83b78285 |
* Atomic memslot updates for KVM (Emanuele, David)
* Always send errors to logfile when daemonized (Greg) * Add support for IDE CompactFlash card (Lubomir) * First round of build system cleanups (myself) * First round of feature removals (myself) * Reduce "qemu/accel.h" inclusion (Philippe) -----BEGIN PGP SIGNATURE----- iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmO3Ym0UHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroNYmwf+LHEw+4T0fk1+2NfgIzH3+8s1EqDm Ai56EjxO/p5NUptflXAnhn4P3LawswmmNE0ZIFFFBgwG5E9L+Jj/u5efuLu4uYPg bboEBDn8nxSNN2l08u9TyS6kSWSxbwwrs7i2+V+4uQIlVIcCHu+A0vpXns4vWwY0 zZGF8CgJKDQdPIxdXrH8+6/xtadQ8uDkYsAWDiY/nhozCsCUTAZGTXWEQbHJLARI Z4X+Cmz/NFB9G4ka6K/y0HbQw99KA8G/EMPUSglN0ya10yjpyzrmeI7IlIves+5U 8lhCZXyBhaV9GXlIK1vIgEXlHf83C19a+v0DpW0bpxK631n2VR5y3CArBg== =2Koq -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * Atomic memslot updates for KVM (Emanuele, David) * Always send errors to logfile when daemonized (Greg) * Add support for IDE CompactFlash card (Lubomir) * First round of build system cleanups (myself) * First round of feature removals (myself) * Reduce "qemu/accel.h" inclusion (Philippe) # gpg: Signature made Thu 05 Jan 2023 23:51:09 GMT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits) i386: SGX: remove deprecated member of SGXInfo target/i386: Add SGX aex-notify and EDECCSSA support util: remove support -chardev tty and -chardev parport util: remove support for hex numbers with a scaling suffix KVM: remove support for kernel-irqchip=off docs: do not talk about past removal as happening in the future meson: accept relative symlinks in "meson introspect --installed" data meson: cleanup compiler detection meson: support meson 0.64 -Doptimization=plain configure: test all warnings tests/qapi-schema: remove Meson workaround meson: cleanup dummy-cpus.c rules meson: tweak hardening options for Windows configure: remove backwards-compatibility and obsolete options configure: preserve qemu-ga variables configure: cleanup $cpu tests configure: remove dead function configure: remove useless write_c_skeleton ide: Add "ide-cf" driver, a CompactFlash card ide: Add 8-bit data mode ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Yicong Yang
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30f71c4afb |
tests: acpi: aarch64: Add *.topology tables
Add *.topology tables for the aarch64's topology test and empty bios-tables-test-allowed-diff.h The disassembled differences between actual and expected PPTT (the table which we actually care about): +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20180105 (64-bit version) + * Copyright (c) 2000 - 2018 Intel Corporation + * + * Disassembly of /tmp/aml-WUN4U1, Tue Nov 1 09:51:52 2022 + * + * ACPI Data Table [PPTT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table] +[004h 0004 4] Table Length : 00000150 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 7C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + + +[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node] +[025h 0037 1] Length : 14 +[026h 0038 2] Reserved : 0000 +[028h 0040 4] Flags (decoded below) : 00000001 + Physical package : 1 + ACPI Processor ID valid : 0 +[02Ch 0044 4] Parent : 00000000 +[030h 0048 4] ACPI Processor ID : 00000000 +[034h 0052 4] Private Resource Number : 00000000 + +[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node] +[039h 0057 1] Length : 14 +[03Ah 0058 2] Reserved : 0000 +[03Ch 0060 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[040h 0064 4] Parent : 00000024 +[044h 0068 4] ACPI Processor ID : 00000000 +[048h 0072 4] Private Resource Number : 00000000 + +[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node] +[04Dh 0077 1] Length : 14 +[04Eh 0078 2] Reserved : 0000 +[050h 0080 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[054h 0084 4] Parent : 00000038 +[058h 0088 4] ACPI Processor ID : 00000000 +[05Ch 0092 4] Private Resource Number : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Hierarchy Node] +[061h 0097 1] Length : 14 +[062h 0098 2] Reserved : 0000 +[064h 0100 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[068h 0104 4] Parent : 0000004C +[06Ch 0108 4] ACPI Processor ID : 00000000 +[070h 0112 4] Private Resource Number : 00000000 + +[074h 0116 1] Subtable Type : 00 [Processor Hierarchy Node] +[075h 0117 1] Length : 14 +[076h 0118 2] Reserved : 0000 +[078h 0120 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[07Ch 0124 4] Parent : 0000004C +[080h 0128 4] ACPI Processor ID : 00000001 +[084h 0132 4] Private Resource Number : 00000000 + +[088h 0136 1] Subtable Type : 00 [Processor Hierarchy Node] +[089h 0137 1] Length : 14 +[08Ah 0138 2] Reserved : 0000 +[08Ch 0140 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[090h 0144 4] Parent : 00000038 +[094h 0148 4] ACPI Processor ID : 00000001 +[098h 0152 4] Private Resource Number : 00000000 + +[09Ch 0156 1] Subtable Type : 00 [Processor Hierarchy Node] +[09Dh 0157 1] Length : 14 +[09Eh 0158 2] Reserved : 0000 +[0A0h 0160 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0A4h 0164 4] Parent : 00000088 +[0A8h 0168 4] ACPI Processor ID : 00000002 +[0ACh 0172 4] Private Resource Number : 00000000 + +[0B0h 0176 1] Subtable Type : 00 [Processor Hierarchy Node] +[0B1h 0177 1] Length : 14 +[0B2h 0178 2] Reserved : 0000 +[0B4h 0180 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0B8h 0184 4] Parent : 00000088 +[0BCh 0188 4] ACPI Processor ID : 00000003 +[0C0h 0192 4] Private Resource Number : 00000000 + +[0C4h 0196 1] Subtable Type : 00 [Processor Hierarchy Node] +[0C5h 0197 1] Length : 14 +[0C6h 0198 2] Reserved : 0000 +[0C8h 0200 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[0CCh 0204 4] Parent : 00000024 +[0D0h 0208 4] ACPI Processor ID : 00000001 +[0D4h 0212 4] Private Resource Number : 00000000 + +[0D8h 0216 1] Subtable Type : 00 [Processor Hierarchy Node] +[0D9h 0217 1] Length : 14 +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[0E0h 0224 4] Parent : 000000C4 +[0E4h 0228 4] ACPI Processor ID : 00000000 +[0E8h 0232 4] Private Resource Number : 00000000 + +[0ECh 0236 1] Subtable Type : 00 [Processor Hierarchy Node] +[0EDh 0237 1] Length : 14 +[0EEh 0238 2] Reserved : 0000 +[0F0h 0240 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[0F4h 0244 4] Parent : 000000D8 +[0F8h 0248 4] ACPI Processor ID : 00000004 +[0FCh 0252 4] Private Resource Number : 00000000 + +[100h 0256 1] Subtable Type : 00 [Processor Hierarchy Node] +[101h 0257 1] Length : 14 +[102h 0258 2] Reserved : 0000 +[104h 0260 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[108h 0264 4] Parent : 000000D8 +[10Ch 0268 4] ACPI Processor ID : 00000005 +[110h 0272 4] Private Resource Number : 00000000 + +[114h 0276 1] Subtable Type : 00 [Processor Hierarchy Node] +[115h 0277 1] Length : 14 +[116h 0278 2] Reserved : 0000 +[118h 0280 4] Flags (decoded below) : 00000000 + Physical package : 0 + ACPI Processor ID valid : 0 +[11Ch 0284 4] Parent : 000000C4 +[120h 0288 4] ACPI Processor ID : 00000001 +[124h 0292 4] Private Resource Number : 00000000 + +[128h 0296 1] Subtable Type : 00 [Processor Hierarchy Node] +[129h 0297 1] Length : 14 +[12Ah 0298 2] Reserved : 0000 +[12Ch 0300 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[130h 0304 4] Parent : 00000114 +[134h 0308 4] ACPI Processor ID : 00000006 +[138h 0312 4] Private Resource Number : 00000000 + +[13Ch 0316 1] Subtable Type : 00 [Processor Hierarchy Node] +[13Dh 0317 1] Length : 14 +[13Eh 0318 2] Reserved : 0000 +[140h 0320 4] Flags (decoded below) : 0000000E + Physical package : 0 + ACPI Processor ID valid : 1 +[144h 0324 4] Parent : 00000114 +[148h 0328 4] ACPI Processor ID : 00000007 +[14Ch 0332 4] Private Resource Number : 00000000 + +Raw Table Data: Length 336 (0x150) + + 0000: 50 50 54 54 50 01 00 00 02 7C 42 4F 43 48 53 20 // PPTTP....|BOCHS + 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC + 0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $............... + 0050: 00 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8........... + 0060: 00 14 00 00 0E 00 00 00 4C 00 00 00 00 00 00 00 // ........L....... + 0070: 00 00 00 00 00 14 00 00 0E 00 00 00 4C 00 00 00 // ............L... + 0080: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 0090: 38 00 00 00 01 00 00 00 00 00 00 00 00 14 00 00 // 8............... + 00A0: 0E 00 00 00 88 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00B0: 00 14 00 00 0E 00 00 00 88 00 00 00 03 00 00 00 // ................ + 00C0: 00 00 00 00 00 14 00 00 00 00 00 00 24 00 00 00 // ............$... + 00D0: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................ + 00E0: C4 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // ................ + 00F0: 0E 00 00 00 D8 00 00 00 04 00 00 00 00 00 00 00 // ................ + 0100: 00 14 00 00 0E 00 00 00 D8 00 00 00 05 00 00 00 // ................ + 0110: 00 00 00 00 00 14 00 00 00 00 00 00 C4 00 00 00 // ................ + 0120: 01 00 00 00 00 00 00 00 00 14 00 00 0E 00 00 00 // ................ + 0130: 14 01 00 00 06 00 00 00 00 00 00 00 00 14 00 00 // ................ + 0140: 0E 00 00 00 14 01 00 00 07 00 00 00 00 00 00 00 // ................ Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-7-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Yicong Yang
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46bda3e4de |
tests: acpi: aarch64: Add topology test for aarch64
Add test for aarch64's ACPI topology building for all the supported levels. Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Tested-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-6-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Yicong Yang
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47a86db4b4 |
tests: acpi: Add and whitelist *.topology blobs
Add and whitelist *.topology blobs, prepares for the aarch64's ACPI topology building test. Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-5-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Yicong Yang
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e7d0bec940 |
tests: virt: Update expected ACPI tables for virt test
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/PPTT, Tue Nov 1 09:29:12 2022
+ * Disassembly of /tmp/aml-DIIGV1, Tue Nov 1 09:29:12 2022
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table]
-[004h 0004 4] Table Length : 00000060
+[004h 0004 4] Table Length : 0000004C
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 48
+[009h 0009 1] Checksum : A8
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
[028h 0040 4] Flags (decoded below) : 00000001
Physical package : 1
ACPI Processor ID valid : 0
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 00000000
+[03Ch 0060 4] Flags (decoded below) : 0000000A
Physical package : 0
- ACPI Processor ID valid : 0
+ ACPI Processor ID valid : 1
[040h 0064 4] Parent : 00000024
[044h 0068 4] ACPI Processor ID : 00000000
[048h 0072 4] Private Resource Number : 00000000
-[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
-[04Dh 0077 1] Length : 14
-[04Eh 0078 2] Reserved : 0000
-[050h 0080 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[054h 0084 4] Parent : 00000038
-[058h 0088 4] ACPI Processor ID : 00000000
-[05Ch 0092 4] Private Resource Number : 00000000
-
-Raw Table Data: Length 96 (0x60)
+Raw Table Data: Length 76 (0x4C)
- 0000: 50 50 54 54 60 00 00 00 02 48 42 4F 43 48 53 20 // PPTT`....HBOCHS
+ 0000: 50 50 54 54 4C 00 00 00 02 A8 42 4F 43 48 53 20 // PPTTL.....BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
- 0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
- 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
+ 0040: 24 00 00 00 00 00 00 00 00 00 00 00 // $...........
PPTT.acpihmatvirt is also updated:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of tests/data/acpi/virt/PPTT.acpihmatvirt, Wed Dec 28 15:36:06 2022
+ * Disassembly of /tmp/aml-IPKJX1, Wed Dec 28 15:36:06 2022
*
* ACPI Data Table [PPTT]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "PPTT" [Processor Properties Topology Table]
-[004h 0004 4] Table Length : 000000C4
+[004h 0004 4] Table Length : 0000009C
[008h 0008 1] Revision : 02
-[009h 0009 1] Checksum : 9E
+[009h 0009 1] Checksum : FE
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 1] Subtable Type : 00 [Processor Hierarchy Node]
[025h 0037 1] Length : 14
[026h 0038 2] Reserved : 0000
[028h 0040 4] Flags (decoded below) : 00000001
Physical package : 1
ACPI Processor ID valid : 0
[02Ch 0044 4] Parent : 00000000
[030h 0048 4] ACPI Processor ID : 00000000
[034h 0052 4] Private Resource Number : 00000000
[038h 0056 1] Subtable Type : 00 [Processor Hierarchy Node]
[039h 0057 1] Length : 14
[03Ah 0058 2] Reserved : 0000
-[03Ch 0060 4] Flags (decoded below) : 00000000
+[03Ch 0060 4] Flags (decoded below) : 0000000A
Physical package : 0
- ACPI Processor ID valid : 0
+ ACPI Processor ID valid : 1
[040h 0064 4] Parent : 00000024
[044h 0068 4] ACPI Processor ID : 00000000
[048h 0072 4] Private Resource Number : 00000000
[04Ch 0076 1] Subtable Type : 00 [Processor Hierarchy Node]
[04Dh 0077 1] Length : 14
[04Eh 0078 2] Reserved : 0000
[050h 0080 4] Flags (decoded below) : 0000000A
Physical package : 0
ACPI Processor ID valid : 1
-[054h 0084 4] Parent : 00000038
-[058h 0088 4] ACPI Processor ID : 00000000
+[054h 0084 4] Parent : 00000024
+[058h 0088 4] ACPI Processor ID : 00000001
[05Ch 0092 4] Private Resource Number : 00000000
[060h 0096 1] Subtable Type : 00 [Processor Hierarchy Node]
[061h 0097 1] Length : 14
[062h 0098 2] Reserved : 0000
-[064h 0100 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[068h 0104 4] Parent : 00000038
+[064h 0100 4] Flags (decoded below) : 00000001
+ Physical package : 1
+ ACPI Processor ID valid : 0
+[068h 0104 4] Parent : 00000000
[06Ch 0108 4] ACPI Processor ID : 00000001
[070h 0112 4] Private Resource Number : 00000000
[074h 0116 1] Subtable Type : 00 [Processor Hierarchy Node]
[075h 0117 1] Length : 14
[076h 0118 2] Reserved : 0000
-[078h 0120 4] Flags (decoded below) : 00000001
- Physical package : 1
- ACPI Processor ID valid : 0
-[07Ch 0124 4] Parent : 00000000
-[080h 0128 4] ACPI Processor ID : 00000001
+[078h 0120 4] Flags (decoded below) : 0000000A
+ Physical package : 0
+ ACPI Processor ID valid : 1
+[07Ch 0124 4] Parent : 00000060
+[080h 0128 4] ACPI Processor ID : 00000002
[084h 0132 4] Private Resource Number : 00000000
[088h 0136 1] Subtable Type : 00 [Processor Hierarchy Node]
[089h 0137 1] Length : 14
[08Ah 0138 2] Reserved : 0000
-[08Ch 0140 4] Flags (decoded below) : 00000000
- Physical package : 0
- ACPI Processor ID valid : 0
-[090h 0144 4] Parent : 00000074
-[094h 0148 4] ACPI Processor ID : 00000000
-[098h 0152 4] Private Resource Number : 00000000
-
-[09Ch 0156 1] Subtable Type : 00 [Processor Hierarchy Node]
-[09Dh 0157 1] Length : 14
-[09Eh 0158 2] Reserved : 0000
-[0A0h 0160 4] Flags (decoded below) : 0000000A
- Physical package : 0
- ACPI Processor ID valid : 1
-[0A4h 0164 4] Parent : 00000088
-[0A8h 0168 4] ACPI Processor ID : 00000002
-[0ACh 0172 4] Private Resource Number : 00000000
-
-[0B0h 0176 1] Subtable Type : 00 [Processor Hierarchy Node]
-[0B1h 0177 1] Length : 14
-[0B2h 0178 2] Reserved : 0000
-[0B4h 0180 4] Flags (decoded below) : 0000000A
+[08Ch 0140 4] Flags (decoded below) : 0000000A
Physical package : 0
ACPI Processor ID valid : 1
-[0B8h 0184 4] Parent : 00000088
-[0BCh 0188 4] ACPI Processor ID : 00000003
-[0C0h 0192 4] Private Resource Number : 00000000
+[090h 0144 4] Parent : 00000060
+[094h 0148 4] ACPI Processor ID : 00000003
+[098h 0152 4] Private Resource Number : 00000000
-Raw Table Data: Length 196 (0xC4)
+Raw Table Data: Length 156 (0x9C)
- 0000: 50 50 54 54 C4 00 00 00 02 9E 42 4F 43 48 53 20 // PPTT......BOCHS
+ 0000: 50 50 54 54 9C 00 00 00 02 FE 42 4F 43 48 53 20 // PPTT......BOCHS
0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC
0020: 01 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0030: 00 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
0040: 24 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // $...............
- 0050: 0A 00 00 00 38 00 00 00 00 00 00 00 00 00 00 00 // ....8...........
- 0060: 00 14 00 00 0A 00 00 00 38 00 00 00 01 00 00 00 // ........8.......
- 0070: 00 00 00 00 00 14 00 00 01 00 00 00 00 00 00 00 // ................
- 0080: 01 00 00 00 00 00 00 00 00 14 00 00 00 00 00 00 // ................
- 0090: 74 00 00 00 00 00 00 00 00 00 00 00 00 14 00 00 // t...............
- 00A0: 0A 00 00 00 88 00 00 00 02 00 00 00 00 00 00 00 // ................
- 00B0: 00 14 00 00 0A 00 00 00 88 00 00 00 03 00 00 00 // ................
- 00C0: 00 00 00 00 // ....
+ 0050: 0A 00 00 00 24 00 00 00 01 00 00 00 00 00 00 00 // ....$...........
+ 0060: 00 14 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0070: 00 00 00 00 00 14 00 00 0A 00 00 00 60 00 00 00 // ............`...
+ 0080: 02 00 00 00 00 00 00 00 00 14 00 00 0A 00 00 00 // ................
+ 0090: 60 00 00 00 03 00 00 00 00 00 00 00 // `...........
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Message-Id: <20221229065513.55652-4-yangyicong@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Yicong Yang
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3cce48d333 |
tests: virt: Allow changes to PPTT test table
Allow changes to test/data/acpi/virt/PPTT*, prepare to change the building policy of the cluster topology. Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Message-Id: <20221229065513.55652-2-yangyicong@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Markus Armbruster
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edf5ca5dbe |
include/hw/pci: Split pci_device.h off pci.h
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Peter Maydell
|
052e6534c4 |
First RISC-V PR for QEMU 8.0
* Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmO3b5sACgkQIeENKd+X cFTD8Af+L0OaGzE4C0jil7LdITFKk7ltdTg3yw84ZBvIxrEWMWlt5Yj3Ez5OIPbY WpPmCLoJ9XM/5CV5PuPjxcFFExWjXLNeMEvaaT/3/3jPPnA/M/AbZa4hefKRluTg kkvBiOuRMPXiYLki5xAHmjD/1j6SQ8ghylPLxYQqyGq87WZt4Dx9msOTZLVzmmYl 8y9oC8j6yO2UBZYC1TxSkKxFbj+Cp2HmtBZ09tDzwRL6DpRvIlfftiLl8X3awMlK YTzCIrmllc38/+cV9IpQhdXzDUZ1kM7Zy56JbJl3XOsS4VnUYGmEtrKYpYQ2CKLY /tcmrDKNw1ArWcP1axNN8FHfhy1FyQ== =SH+C -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 8.0 * Fix PMP propagation for tlb * Collection of bug fixes * Bump the OpenTitan supported version * Add smstateen support * Support native debug icount trigger * Remove the redundant ipi-id property in the virt machine * Support cache-related PMU events in virtual mode * Add some missing PolarFire SoC io regions * Fix mret exception cause when no pmp rule is configured * Fix bug where disabling compressed instructions would crash QEMU * Add Zawrs ISA extension support * A range of code refactoring and cleanups # gpg: Signature made Fri 06 Jan 2023 00:47:23 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230106' of https://github.com/alistair23/qemu: (43 commits) hw/intc: sifive_plic: Fix the pending register range check hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0 hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev" hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC hw/intc: sifive_plic: Update "num-sources" property default value hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in sifive_plic_realize() hw/intc: sifive_plic: Improve robustness of the PLIC config parser hw/intc: sifive_plic: Drop PLICMode_H hw/riscv: spike: Remove misleading comments hw/riscv: Sort machines Kconfig options in alphabetical order hw/riscv: Fix opentitan dependency to SIFIVE_PLIC hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC RISC-V: Add Zawrs ISA extension support target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+ target/riscv: Simplify helper_sret() a little bit target/riscv: Set pc_succ_insn for !rvc illegal insn ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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aaa90fede5 |
Fix race conditions in new user-only vma tracking.
Add tcg backend paired register allocation. Cleanup tcg backend function call abi. -----BEGIN PGP SIGNATURE----- iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmO3kZEdHHJpY2hhcmQu aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/JpwgAj9kwpiWehGWrpQp9 rbEL+Fsx+SDhnoLVpF6nmSB1nkDqdgkdnhyRaLX9wM69bnocsGppZ5sd57J/cH3m WiODVVbWP80WHonx5EN4htQv99TZWqVmXVl11DwOfsRUmINl4GG4kvHOOABd8hdc 39eRgGBBMyMShc6MUJiToyjEAcZPcGAiHkSW9YDGbvzhlloNWh46eLP1bdW3UJWK UiEwPpXqg+L0V8nuuQnSFoPr5FIJmmoTeiGCRHXtvgOT7J8/6eKUESpfcKkHq1ye dwcJQATuZip3+hyCCVveiZ86TQ81RMp9en1qw+HVzfed1Ial3Tk+tqiDqZJFm25b GMpa5g== =OjPl -----END PGP SIGNATURE----- Merge tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu into staging Fix race conditions in new user-only vma tracking. Add tcg backend paired register allocation. Cleanup tcg backend function call abi. # gpg: Signature made Fri 06 Jan 2023 03:12:17 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230105' of https://gitlab.com/rth7680/qemu: (47 commits) tests/tcg/multiarch: add vma-pthread.c accel/tcg: Handle false negative lookup in page_check_range accel/tcg: Use g_free_rcu for user-exec interval trees accel/tcg: Fix tb_invalidate_phys_page_unwind tcg: Add TCGHelperInfo argument to tcg_out_call tcg/aarch64: Merge tcg_out_callr into tcg_out_call tcg: Move ffi_cif pointer into TCGHelperInfo tcg: Factor init_ffi_layouts() out of tcg_context_init() tcg: Convert typecode_to_ffi from array to function tcg: Reorg function calls tcg: Use output_pref wrapper function tcg: Vary the allocation size for TCGOp tcg: Pass number of arguments to tcg_emit_op() / tcg_op_insert_*() accel/tcg/plugin: Use copy_op in append_{udata,mem}_cb accel/tcg/plugin: Avoid duplicate copy in copy_call accel/tcg/plugin: Don't search for the function pointer index tcg: Use TCG_CALL_ARG_EVEN for TCI special case tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Peter Maydell
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171033e8db |
Hexagon update: patches from several folks
-----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmO3Cl8ACgkQewJE+xLe RCKopQf/eVpmA04C792MIYHJnAaASbXZ1FA2Q33l9zrPt9V5oL0cer+rNPlqwVIb jUdFLrT6ppe3jgkzeZVzLTGoNiLO1BnpH3+NV5ZpnMBON4g6/uyagRJekvb5xcDw a832LM77zWrSQbV+Z3C0sn87j7u0YFYiXtya3mJUv6iSfKZnR4bGZH+LW2dOrnXn +uMGnjjUQ2Ac7mvHTnrtooVUNhgRpTq4tMBwl1mE/hacUuejBjDgMLHDb6e4yPC7 g0/BuMB1ygBYFDINJ9El5oD0JtYHZjHOX4TKs6i0oXntoeveut62oGRwgLrk8eRe lwKiEvFNrz/RYmCIy8Pz7s+5HQUgqA== =/i3r -----END PGP SIGNATURE----- Merge tag 'pull-hex-20230105' of https://github.com/quic/qemu into staging Hexagon update: patches from several folks # gpg: Signature made Thu 05 Jan 2023 17:35:27 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20230105' of https://github.com/quic/qemu: Update scripts/meson-buildoptions.sh Hexagon (target/hexagon) implement mutability mask for GPRs target/hexagon: suppress unused variable warning target/hexagon/idef-parser: fix two typos in README tests/tcg/hexagon: fix underspecifed asm constraints target/hexagon: rename aliased register HEX_REG_P3_0 linux-user/hexagon: fix signal context save & restore Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Richard Henderson
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ec2918b467 |
target/riscv: Set pc_succ_insn for !rvc illegal insn
Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com> |
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Paolo Bonzini
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8b902e3d23 |
util: remove support for hex numbers with a scaling suffix
This was deprecated in 6.0 and can now be removed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Paolo Bonzini
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7bef93ff06 |
tests/qapi-schema: remove Meson workaround
The referenced issue has been fixed since version 0.61, so remove the workaround. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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Peter Maydell
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d365cb0b9d |
target-arm queue:
* Implement AArch32 ARMv8-R support * Add Cortex-R52 CPU * fix handling of HLT semihosting in system mode * hw/timer/ixm_epit: cleanup and fix bug in compare handling * target/arm: Coding style fixes * target/arm: Clean up includes * nseries: minor code cleanups * target/arm: align exposed ID registers with Linux * hw/arm/smmu-common: remove unnecessary inlines * i.MX7D: Handle GPT timers * i.MX7D: Connect IRQs to GPIO devices * i.MX6UL: Add a specific GPT timer instance * hw/net: Fix read of uninitialized memory in imx_fec -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmO2/iYZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3sy1EACPsxR5R19BbfwuR3e2VKrA 3ltc1ZwiEiDzKE0YJ+VL8zSyzNKFs0OD4O+ZOBPu5PegwhLdH5QI5QrhkRwlWr6T XJfNDF+8oUUIlNYeD9iSOiZt+W7cnaWrHoM4Oga3O610eS6f0hGmfVxlXUxUfT/4 3x/MKcSXI4SnwXuXrxmqmTm7sVCXP8cbqrIZzN5VUo341B1uqQ5bp1hRmiLt+cvY pnCk3MgYCuZAXRQrLShJkFeu3lJ/W89DVAY5v5+VAMR3jD/tTvQ5bP4HdBMJP4RY AyoI/4cmlAnvOq4Yr8wKdWo7/fgkj9sTHV11sRWkiOdKhLZe9aNYnv1Bd2COhmvH gJcWZ8SNpJ364iRoQPy1PeKxuSMQaesUKWXkvkqjsaGKD9gr2QjTpI3yN6wU3O5+ lT4wGsDMHDhpQml2r19+D3XGm5oA+t2sr1/27WjKBDYopTtZF/KuJ1xVMnIRxzJW M+V3BcM4RPivmv0a+ICA6f1WwE59EeBBzOfZ+VjBpnQAfTv9HRN1yCIVWRN8hIiz cC/iuY6tGxpdZf965fYCIj5cZ2OmCbIw1mh5hUSLDIaCd9+qXl7cgT7stpLar7kA tYDazF2J3v+XqUeyWtPndzAFdgr4rLNH9Q9kDKS9fyXOspIFqv6bBhAMMxiiTbT5 zj5Y2K1lAyHLTTwWmcNruw== =b/pm -----END PGP SIGNATURE----- Merge tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement AArch32 ARMv8-R support * Add Cortex-R52 CPU * fix handling of HLT semihosting in system mode * hw/timer/ixm_epit: cleanup and fix bug in compare handling * target/arm: Coding style fixes * target/arm: Clean up includes * nseries: minor code cleanups * target/arm: align exposed ID registers with Linux * hw/arm/smmu-common: remove unnecessary inlines * i.MX7D: Handle GPT timers * i.MX7D: Connect IRQs to GPIO devices * i.MX6UL: Add a specific GPT timer instance * hw/net: Fix read of uninitialized memory in imx_fec # gpg: Signature made Thu 05 Jan 2023 16:43:18 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230105' of https://git.linaro.org/people/pmaydell/qemu-arm: (34 commits) hw/net: Fix read of uninitialized memory in imx_fec. i.MX7D: Connect IRQs to GPIO devices. i.MX6UL: Add a specific GPT timer instance for the i.MX6UL i.MX7D: Compute clock frequency for the fixed frequency clocks. i.MX7D: Connect GPT timers to IRQ hw/arm/smmu-common: Avoid using inlined functions with external linkage hw/arm/smmu-common: Reduce smmu_inv_notifiers_mr() scope target/arm: align exposed ID registers with Linux hw/arm/nseries: Silent -Wmissing-field-initializers warning hw/arm/nseries: Constify various read-only arrays hw/input/tsc2xxx: Constify set_transform()'s MouseTransformInfo arg target/arm: cleanup cpu includes target/arm: Remove unused includes from helper.c target/arm: Remove unused includes from m_helper.c target/arm: Fix checkpatch brace errors in helper.c target/arm: Fix checkpatch space errors in helper.c target/arm: Fix checkpatch comment style warnings in helper.c hw/timer/imx_epit: fix compare timer handling hw/timer/imx_epit: remove explicit fields cnt and freq hw/timer/imx_epit: factor out register write handlers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Ilya Leoshkevich
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d4846c33eb |
tests/tcg/multiarch: add vma-pthread.c
Add a test that locklessly changes and exercises page protection bits from various threads. This helps catch race conditions in the VMA handling. Acked-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20221223120252.513319-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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Marco Liebel
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d63aeb3b7e |
Hexagon (target/hexagon) implement mutability mask for GPRs
Some registers are defined to have immutable bits, this commit will implement that behavior. Signed-off-by: Marco Liebel <quic_mliebel@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230105102349.2181856-1-quic_mliebel@quicinc.com> |
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Mukilan Thiyagarajan
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eaee3b6faf |
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail. In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register. In mem_noshuf.c, the register r7 is written to but not specified in the clobber list. Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com> |
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Mukilan Thiyagarajan
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c979d901c8 |
linux-user/hexagon: fix signal context save & restore
This patch fixes the issue originally reported in this thread: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html The root cause of the issue is a bug in the hexagon specific logic for saving & restoring context during signal delivery. The CPU state has two different representations for the predicate registers. The current logic saves & restores only the aliased HEX_REG_P3_O register, which is part of env->gpr[] field in the CPU state, but not the individual byte-level predicate registers (pO, p1, p2, p3) backed by env->pred[]. Since all predicated instructions refer only to the indiviual registers, switching to and back from a signal handler can clobber these registers if the signal handler writes to them causing the normal application code to behave unpredictably when context is restored. In the reported issue with the 'signals' test, since the updated hexagon toolchain had built musl with -O2, the functions called from non_trivial_free were inlined. This meant that the code emitted reused predicate P0 computed in the entry translation block of the function non_trivial_free in one of the child TB as part of an assertion. Since P0 is clobbered by the signal handler in the signals test, the assertion in non_trivial_free fails incorectly. Since musl for hexagon implements the 'abort' function by deliberately writing to memory via null pointer, this causes the test to fail with segmentation fault. This patch modifies the signal context save & restore logic to include the individual p0, p1, p2, p3 and excludes the 32b p3_0 register since its value is derived from the former registers. It also adds a new test case that reliabily reproduces the issue for all four predicate registers. Buglink: https://github.com/quic/toolchain_for_hexagon/issues/6 Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229092006.10709-2-quic_mthiyaga@quicinc.com> |
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Peter Maydell
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d1852caab1 |
Python patch roundup
Mostly CI fixes and some small debugging improvements. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+ber27ys35W+dsvQfe+BBqr8OQ4FAmO16doACgkQfe+BBqr8 OQ6CyBAAnJ3Opkz00uUNZIJndDCi9NdLAFEOYSlUQ/4Vx0WTphKRP/NSwfTsSymj ps6E6op0H8AL5PBDjVAF8CzGK9aHNhhDIahbein/42/OQo9uWWMlOnZYhwx8tfxS 8AuYk3s9HeLkSleSHGA0zJZhNB5BtYKewB9FYNZz07fk9wECAVmSOE20g6KR3Tec Fya+YRrvmjCxovGlxxFVi3c1B37bAS25hV5GlrSXxWtZcodIPUsyNEp03SuFjSj7 EvqrRXI3UdR2cSwd56BFyZJfgkKtoLjQMf/hTC8RPHej4SDnpFW8yuN1N3wiSJLn td+yfdIlqg95mF15a2qhwqp+xINWj2J277tkBwbF3FYwChKlJFavw/Ihv6SJIV0+ 7ddiJ/M6PIqsdkfL+//+oFP4Jnh3sW0T5Aa0AYTe/JSMzhLsiOV4H77PZKlylsIt yzNskXQTyGdjZBAQtabTRS80iiKVuxCslJe9a8SQs1Jgiq6cu2pLt2IOLd+cUO0t ETI8JWA8Jc+aZJ3XNev+hfWHPfpUdu4trO3pIUXTS2GS01+Ku9QZsR7Xllr6aj3G 8+NCP9ApA3k9szJFCM7d3cJ0WNlA4GZhVFSKmFMo56dZ8T0dRp8JJ2E5/XqTFlfi JU2pU/3OVhcXkPjSUPHqXF0ep4KaLxc4Ubc2SDk5BotqwlrDKTs= =/6UU -----END PGP SIGNATURE----- Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging Python patch roundup Mostly CI fixes and some small debugging improvements. # gpg: Signature made Wed 04 Jan 2023 21:04:26 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * tag 'python-pull-request' of https://gitlab.com/jsnow/qemu: python: add 3.11 to supported list iotests/check: Fix typing for sys.exit() value Python: fix flake8 config python/machine: Handle termination cases without QMP python/machine: Add debug logging to key state changes Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Zhuojia Shen
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bc6bd20ee3 |
target/arm: align exposed ID registers with Linux
In CPUID registers exposed to userspace, some registers were missing and some fields were not exposed. This patch aligns exposed ID registers and their fields with what the upstream kernel currently exposes. Specifically, the following new ID registers/fields are exposed to userspace: ID_AA64PFR1_EL1.BT: bits 3-0 ID_AA64PFR1_EL1.MTE: bits 11-8 ID_AA64PFR1_EL1.SME: bits 27-24 ID_AA64ZFR0_EL1.SVEver: bits 3-0 ID_AA64ZFR0_EL1.AES: bits 7-4 ID_AA64ZFR0_EL1.BitPerm: bits 19-16 ID_AA64ZFR0_EL1.BF16: bits 23-20 ID_AA64ZFR0_EL1.SHA3: bits 35-32 ID_AA64ZFR0_EL1.SM4: bits 43-40 ID_AA64ZFR0_EL1.I8MM: bits 47-44 ID_AA64ZFR0_EL1.F32MM: bits 55-52 ID_AA64ZFR0_EL1.F64MM: bits 59-56 ID_AA64SMFR0_EL1.F32F32: bit 32 ID_AA64SMFR0_EL1.B16F32: bit 34 ID_AA64SMFR0_EL1.F16F32: bit 35 ID_AA64SMFR0_EL1.I8I32: bits 39-36 ID_AA64SMFR0_EL1.F64F64: bit 48 ID_AA64SMFR0_EL1.I16I64: bits 55-52 ID_AA64SMFR0_EL1.FA64: bit 63 ID_AA64MMFR0_EL1.ECV: bits 63-60 ID_AA64MMFR1_EL1.AFP: bits 47-44 ID_AA64MMFR2_EL1.AT: bits 35-32 ID_AA64ISAR0_EL1.RNDR: bits 63-60 ID_AA64ISAR1_EL1.FRINTTS: bits 35-32 ID_AA64ISAR1_EL1.BF16: bits 47-44 ID_AA64ISAR1_EL1.DGH: bits 51-48 ID_AA64ISAR1_EL1.I8MM: bits 55-52 ID_AA64ISAR2_EL1.WFxT: bits 3-0 ID_AA64ISAR2_EL1.RPRES: bits 7-4 ID_AA64ISAR2_EL1.GPA3: bits 11-8 ID_AA64ISAR2_EL1.APA3: bits 15-12 The code is also refactored to use symbolic names for ID register fields for better readability and maintainability. The test case in tests/tcg/aarch64/sysregs.c is also updated to match the intended behavior. Signed-off-by: Zhuojia Shen <chaosdefinition@hotmail.com> Message-id: DS7PR12MB6309FB585E10772928F14271ACE79@DS7PR12MB6309.namprd12.prod.outlook.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: use Sn_n_Cn_Cn_n syntax to work with older assemblers that don't recognize id_aa64isar2_el1 and id_aa64mmfr2_el1] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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John Snow
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5bcf18b0ac |
iotests/check: Fix typing for sys.exit() value
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Message-id: 20221203005234.620788-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com> |
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Mukilan Thiyagarajan
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b9052d3634 |
tests/docker: use prebuilt toolchain for debian-hexagon-cross
The current docker image for cross compiling hexagon guests
is manually built since it takes >2 hours to build from source.
This patch:
1. Solves the above issue by using the prebuilt clang
toolchain hosted on CodeLinaro [1] and maintained by QUIC [2].
2. The dockerfile is also switched from multi-stage to single stage
build to allow the CI docker engine to reuse the layer cache.
3. Re-enables the hexagon-cross-container job to be always run in
CI and makes it a non-optional dependency for the
build-user-hexagon job.
The changes for 1 & 2 together bring down the build time to
~3 minutes in GitLab CI when cache is reused and ~9 minutes
when cache cannot be reused.
[1]: https://github.com/CodeLinaro/hexagon-builder
[2]: https://github.com/quic/toolchain_for_hexagon/releases/
Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com>
[AJB: also tweak MAINTAINERS, remove QEMU_JOB_ONLY_FORKS and comment]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20221219144354.11659-1-quic_mthiyaga@quicinc.com>
Message-Id: <20221221090411.1995037-6-alex.bennee@linaro.org>
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Alex Bennée
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2bc6c79417 |
tests/tcg: fix unused variable in linux-test
The latest hexagon compiler picks up that we never consume wcount. Given the name of the #define that rcount checks against is WCOUNT_MAX I figured the check just got missed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221090411.1995037-5-alex.bennee@linaro.org> |
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Peter Maydell
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113f00e387 |
virtio,pc,pci: features, cleanups, fixes
make TCO watchdog work by default part of generic vdpa support asid interrupt for vhost-vdpa added flex bus port DVSEC for cxl misc fixes, cleanups, documentation Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmOi/OQPHG1zdEByZWRo YXQuY29tAAoJECgfDbjSjVRpGCkH/j06y7PEDHfG1MnPoFQIEWKHPyU/FMUe1RCW dRsfVmHZ8Jc1Jy4wVch461QpcIC+WL/Fshzh92G0hVDI2AWzJOxzpWQESmCphJJG Olk/H/ort4ZIrwOynAHDKLzgltoTI91uao3UT7w67NumAgVYYW4Q9ObHm2G3Wmwc fe763NmlObrNYYCIbJw/KiBLrk7M5LaMLPeoRGJefD4MYUAPXy/sUQt61VyuZpuG xFAeDB7/76MXFKJVjccSnZfa8lihOJ5AlvCBTjjY5PbGl8+U1usdd3hOVComYb02 LW4sKLkxe5sycg/bFQdBLpz2lZVlMjpY9nd9YiumIrgLBv70Uf0= =WyvK -----END PGP SIGNATURE----- Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging virtio,pc,pci: features, cleanups, fixes make TCO watchdog work by default part of generic vdpa support asid interrupt for vhost-vdpa added flex bus port DVSEC for cxl misc fixes, cleanups, documentation Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed 21 Dec 2022 12:32:36 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (41 commits) contrib/vhost-user-blk: Replace lseek64 with lseek libvhost-user: Switch to unsigned int for inuse field in struct VuVirtq hw/virtio: Extract QMP related code virtio-qmp.c hw/virtio: Extract config read/write accessors to virtio-config-io.c hw/virtio: Constify qmp_virtio_feature_map_t[] hw/virtio: Guard and restrict scope of qmp_virtio_feature_map_t[] hw/virtio: Rename virtio_ss[] -> specific_virtio_ss[] hw/virtio: Add missing "hw/core/cpu.h" include hw/cxl/device: Add Flex Bus Port DVSEC hw/acpi: Rename tco.c -> ich9_tco.c acpi/tests/avocado/bits: add mformat as one of the dependencies docs/acpi/bits: document BITS_DEBUG environment variable pci: drop redundant PCIDeviceClass::is_bridge field remove DEC 21154 PCI bridge vhost: fix vq dirty bitmap syncing when vIOMMU is enabled acpi/tests/avocado/bits: add SPDX license identifiers for bios bits tests include/hw: attempt to document VirtIO feature variables vhost-user: send set log base message only once vdpa: always start CVQ in SVQ mode if possible vdpa: add shadow_data to vhost_vdpa ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Philippe Mathieu-Daudé
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fbae27e857 |
hw/acpi: Rename tco.c -> ich9_tco.c
tco.c contains the ICH9 implementation of its "total cost of ownership". Rename it accordingly to emphasis this is a part of the ICH9 model. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221212105115.2113-1-philmd@linaro.org> Acked-by: Igor Mammedov <imammedo@redhat.com> |
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Ani Sinha
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ffa175f22d |
acpi/tests/avocado/bits: add mformat as one of the dependencies
mformat is needed by grub-mkrescue and hence, add this as one of the dependencies to run bits tests. This avoids errors such as the following: /var/tmp/acpi-bits-wju6tqoa.tmp/grub-inst-x86_64-efi/bin/grub-mkrescue: 360: mformat: not found Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221203132407.34539-1-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Ani Sinha
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5a37392411 |
acpi/tests/avocado/bits: add SPDX license identifiers for bios bits tests
Added the SPDX license identifiers for biosbits tests. Also added a comment on each of the test scripts to indicate that they run from within the biosbits environment and hence are not subjected to the regular maintenance activities for QEMU and is excluded from the dependency management challenges in the host testing environment. Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Maydell Peter <peter.maydell@linaro.org> Cc: John Snow <jsnow@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: Alex Bennée <alex.bennee@linaro.org> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Michael Tsirkin <mst@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Cc: qemu-trivial@nongnu.org Signed-off-by: Ani Sinha <ani@anisinha.ca> Message-Id: <20221125044138.962137-1-ani@anisinha.ca> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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Daniel P. Berrangé
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a6b6414f0c |
hw/isa: enable TCO watchdog reboot pin strap by default
The TCO watchdog implementation default behaviour from POV of the
guest OS relies on the initial values for two I/O ports:
* TCO1_CNT == 0x0
Since bit 11 (TCO Timer Halt) is clear, the watchdog state
is considered to be initially running
* GCS == 0x20
Since bit 5 (No Reboot) is set, the watchdog will not trigger
when the timer expires
This is a safe default, because the No Reboot bit will prevent the
watchdog from triggering if the guest OS is unaware of its existance,
or is slow in configuring it. When a Linux guest initializes the TCO
watchdog, it will attempt to clear the "No Reboot" flag, and read the
value back. If the clear was honoured, the driver will treat this as
an indicator that the watchdog is functional and create the guest
watchdog device.
QEMU implements a second "no reboot" flag, however, via pin straps
which overrides the behaviour of the guest controlled "no reboot"
flag:
commit
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Richard Henderson
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67ff2186b0 |
accel/tcg: Use interval tree for user-only page tracking
Finish weaning user-only away from PageDesc. Using an interval tree to track page permissions means that we can represent very large regions efficiently. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/290 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/967 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1214 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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Richard Henderson
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0d99d37a82 |
util: Add interval-tree.c
Copy and simplify the Linux kernel's interval_tree_generic.h, instantiating for uint64_t. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
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Peter Maydell
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4f9a4cd37e |
1)
Performance improvement Add pkt and insn to DisasContext Many functions need information from all 3 structures, so merge them together. 2) Bug fix Fix predicated assignment to .tmp and .cur 3) Performance improvement Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat These functions will not be handled by idef-parser 4-11) The final 8 patches improve change-of-flow handling. Currently, we set the PC to a new address before exiting a TB. The ultimate goal is to use direct block chaining. However, several steps are needed along the way. 4) When a packet has more than one change-of-flow (COF) instruction, only the first one taken is considered. The runtime bookkeeping is only needed when there is more than one COF instruction in a packet. 5, 6) Remove PC and next_PC from the runtime state and always use a translation-time constant. Note that next_PC is used by call instructions to set LR and by conditional COF instructions to set the fall-through address. 7, 8, 9) Add helper overrides for COF instructions. In particular, we must distinguish those that use a PC-relative address for the destination. These are candidates for direct block chaining later. 10) Use direct block chaining for packets that have a single PC-relative COF instruction. Instead of generating the code while processing the instruction, we record the effect in DisasContext and generate the code during gen_end_tb. 11) Use direct block chaining for tight loops. We look for TBs that end with an endloop0 that will branch back to the TB start address. 12-21) Instruction definition parser (idef-parser) from rev.ng Parses the instruction semantics and generates TCG -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEENjXHiM5iuR/UxZq0ewJE+xLeRCIFAmOc2BEACgkQewJE+xLe RCKqFwf/U/uWaQiF59OXyLHj9PR/bTf7PmZL12g8MTrntzmtIpRiTQb7ajJaLwyn TcCG9j9Ss6kWBq+LH5TBvstnSN9/3qEgnj2b26y6EAn85mSh6fai4foUPjXFUy7m 2Of0kuc2WKmwxN9C2iw6Hm6pbL3FSnYzKtBuSFzYyAIS0doLFT97zE97XnBtTQ4C 49JdNgQW9CKt7cCpKTcQA4N3ZO8LdARdvOtTShX1++qd4Trm0haTGRdaygSrTlS7 Eeqs4nbakKEE6VH2iltPGKX+KHbMCf2ZW7lefxHi+EuzE0DBIVoM64UnalyFfcSU hVMGF15HgAIAjecim0Y4AbPB/zVlEw== =PC9+ -----END PGP SIGNATURE----- Merge tag 'pull-hex-20221216-1' of https://github.com/quic/qemu into staging 1) Performance improvement Add pkt and insn to DisasContext Many functions need information from all 3 structures, so merge them together. 2) Bug fix Fix predicated assignment to .tmp and .cur 3) Performance improvement Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat These functions will not be handled by idef-parser 4-11) The final 8 patches improve change-of-flow handling. Currently, we set the PC to a new address before exiting a TB. The ultimate goal is to use direct block chaining. However, several steps are needed along the way. 4) When a packet has more than one change-of-flow (COF) instruction, only the first one taken is considered. The runtime bookkeeping is only needed when there is more than one COF instruction in a packet. 5, 6) Remove PC and next_PC from the runtime state and always use a translation-time constant. Note that next_PC is used by call instructions to set LR and by conditional COF instructions to set the fall-through address. 7, 8, 9) Add helper overrides for COF instructions. In particular, we must distinguish those that use a PC-relative address for the destination. These are candidates for direct block chaining later. 10) Use direct block chaining for packets that have a single PC-relative COF instruction. Instead of generating the code while processing the instruction, we record the effect in DisasContext and generate the code during gen_end_tb. 11) Use direct block chaining for tight loops. We look for TBs that end with an endloop0 that will branch back to the TB start address. 12-21) Instruction definition parser (idef-parser) from rev.ng Parses the instruction semantics and generates TCG # gpg: Signature made Fri 16 Dec 2022 20:41:53 GMT # gpg: using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * tag 'pull-hex-20221216-1' of https://github.com/quic/qemu: (21 commits) target/hexagon: import additional tests target/hexagon: call idef-parser functions target/hexagon: import parser for idef-parser target/hexagon: import lexer for idef-parser target/hexagon: prepare input for the idef-parser target/hexagon: introduce new helper functions target/hexagon: make helper functions non-static target/hexagon: make slot number an unsigned target/hexagon: import README for idef-parser target/hexagon: update MAINTAINERS for idef-parser Hexagon (target/hexagon) Use direct block chaining for tight loops Hexagon (target/hexagon) Use direct block chaining for direct jump/branch Hexagon (target/hexagon) Add overrides for various forms of jump Hexagon (target/hexagon) Add overrides for compound compare and jump Hexagon (target/hexagon) Add overrides for direct call instructions Hexagon (target/hexagon) Remove next_PC from runtime state Hexagon (target/hexagon) Remove PC from the runtime state Hexagon (target/hexagon) Only use branch_taken when packet has multi cof Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Niccolò Izzo
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585a86b104 |
target/hexagon: import additional tests
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Niccolò Izzo <nizzo@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-12-anjo@rev.ng> |
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Taylor Simpson
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8e8a85c14e |
Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These instructions will not be generated by idef-parser, so we override them manually. Test cases added to tests/tcg/hexagon/usr.c Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221108162906.3166-4-tsimpson@quicinc.com> |
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Taylor Simpson
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83853ea0ef |
Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same packet
take the result of the load. However, when the predicate is false,
the value at the start of the packet should be used. After the packet
commits, the .tmp value is dropped, but the .cur value is maintained.
To fix this bug, we preload the original value from the HVX register
into the temporary used for the result.
Test cases added to tests/tcg/hexagon/hvx_misc.c
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221108162906.3166-3-tsimpson@quicinc.com>
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Peter Maydell
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d038d2645a |
Block layer patches
- Code cleanups around block graph modification - Simplify drain - coroutine_fn correctness fixes, including splitting generated coroutine wrappers into co_wrapper (to be called only from non-coroutine context) and co_wrapper_mixed (both coroutine and non-coroutine context) - Introduce a block graph rwlock -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE3D3rFZqa+V09dFb+fwmycsiPL9YFAmObOHIRHGt3b2xmQHJl ZGhhdC5jb20ACgkQfwmycsiPL9b4DQ//VAgplktr9NvX00a/hu4ZXgMyMuwPz36a 0Lfb11hxZM02hN1Re1M/ldzxrQj5ywxatmPH3bwLW/TjlPcXwOHvToF1EwkW/3Ow evmOUOxEH/o7Re8ZrEQEjEg3LdlFBrpRyRNS5qrGK4+38TKsecLYakZdOvYyPujm zpE4uGzG+ZYygyx4OtEhL7bry/iKO3ehGYO3/5IKrpjH+hj1MhYegcUCE7r4eE0G Mmo48ALsxlwStTUx9gUp9jwr5p08k3Jl+ubZnkTPcNZYoyTgX3rOycD8yPoaHoFr bMV6SKPZckueMT1aCTZ2pQl2gJ2ap+YFgJYQ4oyY8powVayZbVFtO9tGO/ZN+IWY zC88tmRMj1KGlgg1R0dUCOfzaJZkk44wZV72U6D3zKuXWBtHVz3WgnlRmD7k4K5Q MhqgqOatSBcD6XajmzMJi6W1xEcMs7yy9/V5e5AsGLKrjX0Z8r8+A6cK18/Hd+4N 9cDkhHET0TccmU2sTgmkqOYXl/VyiU622g1b7E9sjSdzKnqqZ4H0IkFf2G23gVBR 4xgUsftaBaIIRlrp1mHtR8zo7646pQZrZi3RFPx83dJYXpreUtnNNTzlURdnDDfA chvHjrjZ/sz2VKmMHK+PnFVVpxWSAUhHoRUcMV1+EmRGlm9ikuVO4WDBqaG8HHNk vZBm7LpuGGE= =Z9pn -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://repo.or.cz/qemu/kevin into staging Block layer patches - Code cleanups around block graph modification - Simplify drain - coroutine_fn correctness fixes, including splitting generated coroutine wrappers into co_wrapper (to be called only from non-coroutine context) and co_wrapper_mixed (both coroutine and non-coroutine context) - Introduce a block graph rwlock # gpg: Signature made Thu 15 Dec 2022 15:08:34 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * tag 'for-upstream' of https://repo.or.cz/qemu/kevin: (50 commits) block: GRAPH_RDLOCK for functions only called by co_wrappers block: use co_wrapper_mixed_bdrv_rdlock in functions taking the rdlock block-coroutine-wrapper.py: introduce annotations that take the graph rdlock Mark assert_bdrv_graph_readable/writable() GRAPH_RD/WRLOCK graph-lock: TSA annotations for lock/unlock functions block: assert that graph read and writes are performed correctly block: remove unnecessary assert_bdrv_graph_writable() block: wrlock in bdrv_replace_child_noperm block: Fix locking in external_snapshot_prepare() test-bdrv-drain: Fix incorrrect drain assumptions clang-tsa: Add macros for shared locks clang-tsa: Add TSA_ASSERT() macro Import clang-tsa.h async: Register/unregister aiocontext in graph lock list graph-lock: Implement guard macros graph-lock: Introduce a lock to protect block graph operations block: Factor out bdrv_drain_all_begin_nopoll() block/dirty-bitmap: convert coroutine-only functions to co_wrapper block: convert bdrv_create to co_wrapper block-coroutine-wrapper.py: support also basic return types ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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Kevin Wolf
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617f3a9635 |
test-bdrv-drain: Fix incorrrect drain assumptions
The test case assumes that a drain only happens in one specific place where it drains explicitly. This assumption happened to hold true until now, but block layer functions may drain interally (any graph modifications are going to do that through bdrv_graph_wrlock()), so this is incorrect. Make sure that the test code in .drained_begin only runs where we actually want it to run. When scheduling a BH from .drained_begin, we also need to increase the in_flight counter to make sure that the operation is actually completed in time before the node that it works on goes away. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221207131838.239125-10-kwolf@redhat.com> Reviewed-by: Emanuele Giuseppe Esposito <eesposit@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> |
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Kevin Wolf
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2398747128 |
block: Don't poll in bdrv_replace_child_noperm()
In order to make sure that bdrv_replace_child_noperm() doesn't have to poll any more, get rid of the bdrv_parent_drained_begin_single() call. This is possible now because we can require that the parent is already drained through the child in question when the function is called and we don't call the parent drain callbacks more than once. The additional drain calls needed in callers cause the test case to run its code in the drain handler too early (bdrv_attach_child() drains now), so modify it to only enable the code after the test setup has completed. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Message-Id: <20221118174110.55183-15-kwolf@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Signed-off-by: Kevin Wolf <kwolf@redhat.com> |
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Kevin Wolf
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57e05be343 |
block: Call drain callbacks only once
We only need to call both the BlockDriver's callback and the parent
callbacks when going from undrained to drained or vice versa. A second
drain section doesn't make a difference for the driver or the parent,
they weren't supposed to send new requests before and after the second
drain.
One thing that gets in the way is the 'ignore_bds_parents' parameter in
bdrv_do_drained_begin_quiesce() and bdrv_do_drained_end(): It means that
bdrv_drain_all_begin() increases bs->quiesce_counter, but does not
quiesce the parent through BdrvChildClass callbacks. If an additional
drain section is started now, bs->quiesce_counter will be non-zero, but
we would still need to quiesce the parent through BdrvChildClass in
order to keep things consistent (and unquiesce it on the matching
bdrv_drained_end(), even though the counter would not reach 0 yet as
long as the bdrv_drain_all() section is still active).
Instead of keeping track of this, let's just get rid of the parameter.
It was introduced in commit
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Kevin Wolf
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299403aeda |
block: Remove subtree drains
Subtree drains are not used any more. Remove them. After this, BdrvChildClass.attach/detach() don't poll any more. Signed-off-by: Kevin Wolf <kwolf@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20221118174110.55183-11-kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com> |