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target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer)

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Fixes RISU mismatch for "fcvtzs h31, h0, #14".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson 2024-05-24 16:20:18 -07:00 committed by Peter Maydell
parent db36e14501
commit fe84877ed4
1 changed files with 3 additions and 0 deletions
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3
target/arm/tcg/translate-a64.c
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@ -8707,6 +8707,9 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
read_vec_element_i32(s, tcg_op, rn, pass, size);
fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
if (is_scalar) {
if (size == MO_16 && !is_u) {
tcg_gen_ext16u_i32(tcg_op, tcg_op);
}
write_fp_sreg(s, rd, tcg_op);
} else {
write_vec_element_i32(s, tcg_op, rd, pass, size);