From fe84877ed44040dc128362b61dbfd923b851d6ef Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 24 May 2024 16:20:18 -0700 Subject: [PATCH] target/arm: Zero-extend writeback for fp16 FCVTZS (scalar, integer) Fixes RISU mismatch for "fcvtzs h31, h0, #14". Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20240524232121.284515-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4126aaa27e..d97acdbaf9 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8707,6 +8707,9 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, read_vec_element_i32(s, tcg_op, rn, pass, size); fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus); if (is_scalar) { + if (size == MO_16 && !is_u) { + tcg_gen_ext16u_i32(tcg_op, tcg_op); + } write_fp_sreg(s, rd, tcg_op); } else { write_vec_element_i32(s, tcg_op, rd, pass, size);