mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC

Browse Source 
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54
RISC-V cores. Currently the sifive_u machine only populates 4 U54
cores. Update the max cpu number to 5 to reflect the real hardware,
by creating 2 CPU clusters as containers for RISC-V hart arrays to
populate heterogeneous harts.

The cpu nodes in the generated DTS have been updated as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Bin Meng 2019-09-06 09:20:06 -07:00 committed by Palmer Dabbelt
parent f3d47d5804
commit ecdfe393b6
No known key found for this signature in database
GPG Key ID: EF4CA1502CCBAB41
2 changed files with 72 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

92
hw/riscv/sifive_u.c
View File

@ -11,7 +11,7 @@
* 2) PLIC (Platform Level Interrupt Controller) * 2) PLIC (Platform Level Interrupt Controller)
* *
* This board currently generates devicetree dynamically that indicates at least * This board currently generates devicetree dynamically that indicates at least
* two harts. * two harts and up to five harts.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -34,6 +34,7 @@
#include "hw/loader.h" #include "hw/loader.h"
#include "hw/sysbus.h" #include "hw/sysbus.h"
#include "hw/char/serial.h" #include "hw/char/serial.h"
#include "hw/cpu/cluster.h"
#include "target/riscv/cpu.h" #include "target/riscv/cpu.h"
#include "hw/riscv/riscv_hart.h" #include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_plic.h"
@ -70,6 +71,7 @@ static const struct MemmapEntry {
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline) uint64_t mem_size, const char *cmdline)
{ {
MachineState *ms = MACHINE(qdev_get_machine());
void *fdt; void *fdt;
int cpu; int cpu;
uint32_t *cells; uint32_t *cells;
@ -110,15 +112,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
int cpu_phandle = phandle++; int cpu_phandle = phandle++;
nodename = g_strdup_printf("/cpus/cpu@%d", cpu); nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); char *isa;
qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
SIFIVE_U_CLOCK_FREQ); SIFIVE_U_CLOCK_FREQ);
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); /* cpu 0 is the management hart that does not have mmu */
if (cpu != 0) {
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
} else {
isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
}
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
@ -134,8 +142,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename); g_free(nodename);
} }
cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); cells = g_new0(uint32_t, ms->smp.cpus * 4);
for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
nodename = nodename =
g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
@ -153,20 +161,26 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
0x0, memmap[SIFIVE_U_CLINT].base, 0x0, memmap[SIFIVE_U_CLINT].base,
0x0, memmap[SIFIVE_U_CLINT].size); 0x0, memmap[SIFIVE_U_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended", qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells); g_free(cells);
g_free(nodename); g_free(nodename);
plic_phandle = phandle++; plic_phandle = phandle++;
cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);
for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
nodename = nodename =
g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); /* cpu 0 is the management hart that does not have S-mode */
cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); if (cpu == 0) {
cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); cells[0] = cpu_to_be32(intc_phandle);
cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); cells[1] = cpu_to_be32(IRQ_M_EXT);
} else {
cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
}
g_free(nodename); g_free(nodename);
} }
nodename = g_strdup_printf("/soc/interrupt-controller@%lx", nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
@ -176,7 +190,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended", qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg", qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].base,
0x0, memmap[SIFIVE_U_PLIC].size); 0x0, memmap[SIFIVE_U_PLIC].size);
@ -339,12 +353,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
SiFiveUSoCState *s = RISCV_U_SOC(obj); SiFiveUSoCState *s = RISCV_U_SOC(obj);
object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), object_initialize_child(obj, "e-cluster", &s->e_cluster,
TYPE_RISCV_HART_ARRAY, &error_abort, NULL); sizeof(s->e_cluster), TYPE_CPU_CLUSTER,
object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", &error_abort, NULL);
&error_abort); qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort); object_initialize_child(OBJECT(&s->e_cluster), "e-cpus",
&s->e_cpus, sizeof(s->e_cpus),
TYPE_RISCV_HART_ARRAY, &error_abort,
NULL);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
object_initialize_child(obj, "u-cluster", &s->u_cluster,
sizeof(s->u_cluster), TYPE_CPU_CLUSTER,
&error_abort, NULL);
qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
object_initialize_child(OBJECT(&s->u_cluster), "u-cpus",
&s->u_cpus, sizeof(s->u_cpus),
TYPE_RISCV_HART_ARRAY, &error_abort,
NULL);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM); TYPE_CADENCE_GEM);
@ -364,7 +397,19 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
Error *err = NULL; Error *err = NULL;
NICInfo *nd = &nd_table[0]; NICInfo *nd = &nd_table[0];
object_property_set_bool(OBJECT(&s->cpus), true, "realized", object_property_set_bool(OBJECT(&s->e_cpus), true, "realized",
&error_abort);
object_property_set_bool(OBJECT(&s->u_cpus), true, "realized",
&error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
* CPU must exist and have been parented into the cluster before the
* cluster is realized.
*/
object_property_set_bool(OBJECT(&s->e_cluster), true, "realized",
&error_abort);
object_property_set_bool(OBJECT(&s->u_cluster), true, "realized",
&error_abort); &error_abort);
/* boot rom */ /* boot rom */
@ -430,10 +475,7 @@ static void riscv_sifive_u_machine_init(MachineClass *mc)
{ {
mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->desc = "RISC-V Board compatible with SiFive U SDK";
mc->init = riscv_sifive_u_init; mc->init = riscv_sifive_u_init;
/* The real hardware has 5 CPUs, but one of them is a small embedded power mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
* management CPU.
*/
mc->max_cpus = 4;
mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
mc->default_cpus = mc->min_cpus; mc->default_cpus = mc->min_cpus;
} }

6
include/hw/riscv/sifive_u.h
View File

@ -32,7 +32,10 @@ typedef struct SiFiveUSoCState {
SysBusDevice parent_obj; SysBusDevice parent_obj;
/*< public >*/ /*< public >*/
RISCVHartArrayState cpus; CPUClusterState e_cluster;
CPUClusterState u_cluster;
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic; DeviceState *plic;
CadenceGEMState gem; CadenceGEMState gem;
} SiFiveUSoCState; } SiFiveUSoCState;
@ -70,6 +73,7 @@ enum {
}; };
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 #define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
#define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_HART_CONFIG "MS"
#define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_SOURCES 54