ecdfe393b6
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
89 lines
2.2 KiB
C
89 lines
2.2 KiB
C
/*
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* SiFive U series machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_U_H
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#define HW_SIFIVE_U_H
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#include "hw/net/cadence_gem.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_cpu.h"
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#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
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#define RISCV_U_SOC(obj) \
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OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
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typedef struct SiFiveUSoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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CPUClusterState e_cluster;
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CPUClusterState u_cluster;
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RISCVHartArrayState e_cpus;
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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CadenceGEMState gem;
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} SiFiveUSoCState;
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typedef struct SiFiveUState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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SiFiveUSoCState soc;
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void *fdt;
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int fdt_size;
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} SiFiveUState;
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enum {
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SIFIVE_U_DEBUG,
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SIFIVE_U_MROM,
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SIFIVE_U_CLINT,
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SIFIVE_U_PLIC,
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SIFIVE_U_UART0,
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SIFIVE_U_UART1,
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SIFIVE_U_DRAM,
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SIFIVE_U_GEM
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};
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enum {
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SIFIVE_U_UART0_IRQ = 3,
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SIFIVE_U_UART1_IRQ = 4,
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SIFIVE_U_GEM_IRQ = 0x35
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};
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enum {
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SIFIVE_U_CLOCK_FREQ = 1000000000,
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SIFIVE_U_GEM_CLOCK_FREQ = 125000000
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};
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#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
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#define SIFIVE_U_COMPUTE_CPU_COUNT 4
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#define SIFIVE_U_PLIC_HART_CONFIG "MS"
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#define SIFIVE_U_PLIC_NUM_SOURCES 54
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
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#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
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#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
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#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
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#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
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#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
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#endif
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