target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructions
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-5-gaosong@loongson.cn>
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@ -682,7 +682,7 @@ DEF_HELPER_4(vilvh_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vilvh_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vilvh_d, void, env, i32, i32, i32)
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DEF_HELPER_5(vshuf_b, void, env, i32, i32, i32, i32)
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DEF_HELPER_FLAGS_5(vshuf_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_4(vshuf_h, void, env, i32, i32, i32)
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DEF_HELPER_4(vshuf_w, void, env, i32, i32, i32)
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DEF_HELPER_4(vshuf_d, void, env, i32, i32, i32)
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@ -34,20 +34,24 @@ static bool gen_vvvv_ptr(DisasContext *ctx, arg_vvvv *a,
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return gen_vvvv_ptr_vl(ctx, a, 16, fn);
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}
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static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
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void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32,
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TCGv_i32, TCGv_i32))
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static bool gen_vvvv_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
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gen_helper_gvec_4 *fn)
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{
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TCGv_i32 vd = tcg_constant_i32(a->vd);
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TCGv_i32 vj = tcg_constant_i32(a->vj);
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TCGv_i32 vk = tcg_constant_i32(a->vk);
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TCGv_i32 va = tcg_constant_i32(a->va);
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CHECK_SXE;
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func(cpu_env, vd, vj, vk, va);
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tcg_gen_gvec_4_ool(vec_full_offset(a->vd),
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vec_full_offset(a->vj),
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vec_full_offset(a->vk),
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vec_full_offset(a->va),
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oprsz, ctx->vl / 8, 0, fn);
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return true;
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}
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static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
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gen_helper_gvec_4 *fn)
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{
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CHECK_SXE;
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return gen_vvvv_vl(ctx, a, 16, fn);
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}
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static bool gen_vvv(DisasContext *ctx, arg_vvv *a,
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void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
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{
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@ -2899,15 +2899,14 @@ VILVH(vilvh_h, 32, H)
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VILVH(vilvh_w, 64, W)
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VILVH(vilvh_d, 128, D)
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void HELPER(vshuf_b)(CPULoongArchState *env,
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uint32_t vd, uint32_t vj, uint32_t vk, uint32_t va)
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void HELPER(vshuf_b)(void *vd, void *vj, void *vk, void *va, uint32_t desc)
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{
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int i, m;
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VReg temp;
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VReg *Vd = &(env->fpr[vd].vreg);
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VReg *Vj = &(env->fpr[vj].vreg);
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VReg *Vk = &(env->fpr[vk].vreg);
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VReg *Va = &(env->fpr[va].vreg);
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VReg *Vd = (VReg *)vd;
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VReg *Vj = (VReg *)vj;
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VReg *Vk = (VReg *)vk;
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VReg *Va = (VReg *)va;
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m = LSX_LEN/8;
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for (i = 0; i < m ; i++) {
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