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target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructions

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Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-4-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:25:51 +08:00
parent b630aeaae7
commit e2600dad02
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 41 additions and 22 deletions
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16
target/loongarch/helper.h
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@ -528,14 +528,14 @@ DEF_HELPER_4(vfmul_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_d, void, env, i32, i32, i32)
DEF_HELPER_5(vfmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_d, void, env, i32, i32, i32, i32)
DEF_HELPER_FLAGS_6(vfmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vfmax_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmax_d, void, env, i32, i32, i32)

35
target/loongarch/insn_trans/trans_vec.c.inc
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@ -15,6 +15,25 @@
#define CHECK_SXE
#endif
static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
gen_helper_gvec_4_ptr *fn)
{
tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
vec_full_offset(a->vj),
vec_full_offset(a->vk),
vec_full_offset(a->va),
cpu_env,
oprsz, ctx->vl / 8, 0, fn);
return true;
}
static bool gen_vvvv_ptr(DisasContext *ctx, arg_vvvv *a,
gen_helper_gvec_4_ptr *fn)
{
CHECK_SXE;
return gen_vvvv_ptr_vl(ctx, a, 16, fn);
}
static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32,
TCGv_i32, TCGv_i32))
@ -3634,14 +3653,14 @@ TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d)
TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s)
TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d)
TRANS(vfmadd_s, LSX, gen_vvvv, gen_helper_vfmadd_s)
TRANS(vfmadd_d, LSX, gen_vvvv, gen_helper_vfmadd_d)
TRANS(vfmsub_s, LSX, gen_vvvv, gen_helper_vfmsub_s)
TRANS(vfmsub_d, LSX, gen_vvvv, gen_helper_vfmsub_d)
TRANS(vfnmadd_s, LSX, gen_vvvv, gen_helper_vfnmadd_s)
TRANS(vfnmadd_d, LSX, gen_vvvv, gen_helper_vfnmadd_d)
TRANS(vfnmsub_s, LSX, gen_vvvv, gen_helper_vfnmsub_s)
TRANS(vfnmsub_d, LSX, gen_vvvv, gen_helper_vfnmsub_d)
TRANS(vfmadd_s, LSX, gen_vvvv_ptr, gen_helper_vfmadd_s)
TRANS(vfmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfmadd_d)
TRANS(vfmsub_s, LSX, gen_vvvv_ptr, gen_helper_vfmsub_s)
TRANS(vfmsub_d, LSX, gen_vvvv_ptr, gen_helper_vfmsub_d)
TRANS(vfnmadd_s, LSX, gen_vvvv_ptr, gen_helper_vfnmadd_s)
TRANS(vfnmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfnmadd_d)
TRANS(vfnmsub_s, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_s)
TRANS(vfnmsub_d, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_d)
TRANS(vfmax_s, LSX, gen_vvv, gen_helper_vfmax_s)
TRANS(vfmax_d, LSX, gen_vvv, gen_helper_vfmax_d)

12
target/loongarch/vec_helper.c
View File

@ -2129,14 +2129,14 @@ DO_3OP_F(vfmina_s, 32, UW, float32_minnummag)
DO_3OP_F(vfmina_d, 64, UD, float64_minnummag)
#define DO_4OP_F(NAME, BIT, E, FN, flags) \
void HELPER(NAME)(CPULoongArchState *env, \
uint32_t vd, uint32_t vj, uint32_t vk, uint32_t va) \
void HELPER(NAME)(void *vd, void *vj, void *vk, void *va, \
CPULoongArchState *env, uint32_t desc) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
VReg *Va = &(env->fpr[va].vreg); \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
VReg *Va = (VReg *)va; \
\
vec_clear_cause(env); \
for (i = 0; i < LSX_LEN/BIT; i++) { \