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target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call

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The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-8-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2015-09-07 10:39:28 +01:00
parent faacc04161
commit e9ebfbfcf3
1 changed files with 10 additions and 0 deletions
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10
target-arm/arm-semi.c
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@ -58,6 +58,7 @@
#define TARGET_SYS_GET_CMDLINE 0x15 #define TARGET_SYS_GET_CMDLINE 0x15
#define TARGET_SYS_HEAPINFO 0x16 #define TARGET_SYS_HEAPINFO 0x16
#define TARGET_SYS_EXIT 0x18 #define TARGET_SYS_EXIT 0x18
#define TARGET_SYS_SYNCCACHE 0x19
/* ADP_Stopped_ApplicationExit is used for exit(0), /* ADP_Stopped_ApplicationExit is used for exit(0),
* anything else is implemented as exit(1) */ * anything else is implemented as exit(1) */
@ -623,6 +624,15 @@ target_ulong do_arm_semihosting(CPUARMState *env)
ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1; ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
gdb_exit(env, ret); gdb_exit(env, ret);
exit(ret); exit(ret);
case TARGET_SYS_SYNCCACHE:
/* Clean the D-cache and invalidate the I-cache for the specified
* virtual address range. This is a nop for us since we don't
* implement caches. This is only present on A64.
*/
if (is_a64(env)) {
return 0;
}
/* fall through -- invalid for A32/T32 */
default: default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, fprintf, 0); cpu_dump_state(cs, stderr, fprintf, 0);