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target/arm: Implement new VFP fp16 insn VINS

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The fp16 extension includes a new instruction VINS, which copies the
lower 16 bits of a 32-bit source VFP register into the upper 16 bits
of the destination.  Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-20-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-28 19:33:28 +01:00
parent 0a6f4b4cb3
commit e4875e3bcc
2 changed files with 31 additions and 0 deletions
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28
target/arm/translate-vfp.c.inc
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@ -3454,3 +3454,31 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a)
return false;
}
static bool trans_VINS(DisasContext *s, arg_VINS *a)
{
TCGv_i32 rd, rm;
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
/* Insert low half of Vm into high half of Vd */
rm = tcg_temp_new_i32();
rd = tcg_temp_new_i32();
neon_load_reg32(rm, a->vm);
neon_load_reg32(rd, a->vd);
tcg_gen_deposit_i32(rd, rd, rm, 16, 16);
neon_store_reg32(rd, a->vd);
tcg_temp_free_i32(rm);
tcg_temp_free_i32(rd);
return true;
}

3
target/arm/vfp-uncond.decode
View File

@ -74,3 +74,6 @@ VCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
vm=%vm_sp vd=%vd_sp sz=2
VCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
vm=%vm_dp vd=%vd_sp sz=3
VINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \
vd=%vd_sp vm=%vm_sp