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target/mips: Fix ADD.S FPU instruction

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After merging latest QEMU upstream into our CHERI fork,
I noticed that some of the FPU tests in our MIPS baremetal
testsuite [*] started failing.
It turns out commit 1ace099f2a accidentally changed add.s
into a subtract.

[*] https://github.com/CTSRD-CHERI/cheritest

Fixes: 1ace099f2a ("target/mips: fpu: Demacro ADD.<D|S|PS>")
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200703161515.25966-1-Alexander.Richardson@cl.cam.ac.uk>
Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Alex Richardson 2020-07-03 17:15:15 +01:00 committed by Philippe Mathieu-Daudé
parent 9788e8c9b6
commit dda97e385b
1 changed files with 1 additions and 1 deletions
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target/mips/fpu_helper.c
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@ -1221,7 +1221,7 @@ uint32_t helper_float_add_s(CPUMIPSState *env,
{ {
uint32_t wt2; uint32_t wt2;
wt2 = float32_sub(fst0, fst1, &env->active_fpu.fp_status); wt2 = float32_add(fst0, fst1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC()); update_fcr31(env, GETPC());
return wt2; return wt2;
} }