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tcg/i386: Optimize cmpsel with constant 0 operand 3.

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These can be simplified to and/andc, avoiding the load of
the zero into a register.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-09-06 22:01:12 -07:00
parent e58b977238
commit d8387f0ee0
3 changed files with 27 additions and 8 deletions
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2
tcg/i386/tcg-target-con-set.h
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@ -50,7 +50,7 @@ C_N1_I2(r, r, r)
C_N1_I2(r, r, rW) C_N1_I2(r, r, rW)
C_O1_I3(x, 0, x, x) C_O1_I3(x, 0, x, x)
C_O1_I3(x, x, x, x) C_O1_I3(x, x, x, x)
C_O1_I4(x, x, x, x, x) C_O1_I4(x, x, x, xO, x)
C_O1_I4(r, r, reT, r, 0) C_O1_I4(r, r, reT, r, 0)
C_O1_I4(r, r, r, ri, ri) C_O1_I4(r, r, r, ri, ri)
C_O2_I1(r, r, L) C_O2_I1(r, r, L)

1
tcg/i386/tcg-target-con-str.h
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@ -28,6 +28,7 @@ REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
*/ */
CONST('e', TCG_CT_CONST_S32) CONST('e', TCG_CT_CONST_S32)
CONST('I', TCG_CT_CONST_I32) CONST('I', TCG_CT_CONST_I32)
CONST('O', TCG_CT_CONST_ZERO)
CONST('T', TCG_CT_CONST_TST) CONST('T', TCG_CT_CONST_TST)
CONST('W', TCG_CT_CONST_WSZ) CONST('W', TCG_CT_CONST_WSZ)
CONST('Z', TCG_CT_CONST_U32) CONST('Z', TCG_CT_CONST_U32)

32
tcg/i386/tcg-target.c.inc
View File

@ -133,6 +133,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_CT_CONST_I32 0x400 #define TCG_CT_CONST_I32 0x400
#define TCG_CT_CONST_WSZ 0x800 #define TCG_CT_CONST_WSZ 0x800
#define TCG_CT_CONST_TST 0x1000 #define TCG_CT_CONST_TST 0x1000
#define TCG_CT_CONST_ZERO 0x2000
/* Registers used with L constraint, which are the first argument /* Registers used with L constraint, which are the first argument
registers on x86_64, and two random call clobbered registers on registers on x86_64, and two random call clobbered registers on
@ -226,6 +227,9 @@ static bool tcg_target_const_match(int64_t val, int ct,
if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
return 1; return 1;
} }
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
return 0; return 0;
} }
@ -3119,13 +3123,27 @@ static void tcg_out_cmpsel_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg v0, TCGReg c1, TCGReg c2, TCGReg v0, TCGReg c1, TCGReg c2,
TCGReg v3, TCGReg v4, TCGCond cond) TCGReg v3, TCGReg v4, TCGCond cond)
{ {
if (tcg_out_cmp_vec_noinv(s, type, vece, TCG_TMP_VEC, c1, c2, cond)) { bool inv = tcg_out_cmp_vec_noinv(s, type, vece, TCG_TMP_VEC, c1, c2, cond);
TCGReg swap = v3;
v3 = v4; /*
v4 = swap; * Since XMM0 is 16, the only way we get 0 into V3
* is via the constant zero constraint.
*/
if (!v3) {
if (inv) {
tcg_out_vex_modrm_type(s, OPC_PAND, v0, TCG_TMP_VEC, v4, type);
} else {
tcg_out_vex_modrm_type(s, OPC_PANDN, v0, TCG_TMP_VEC, v4, type);
}
} else {
if (inv) {
TCGReg swap = v3;
v3 = v4;
v4 = swap;
}
tcg_out_vex_modrm_type(s, OPC_VPBLENDVB, v0, v4, v3, type);
tcg_out8(s, (TCG_TMP_VEC - TCG_REG_XMM0) << 4);
} }
tcg_out_vex_modrm_type(s, OPC_VPBLENDVB, v0, v4, v3, type);
tcg_out8(s, (TCG_TMP_VEC - TCG_REG_XMM0) << 4);
} }
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
@ -3716,7 +3734,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_bitsel_vec: case INDEX_op_bitsel_vec:
return C_O1_I3(x, x, x, x); return C_O1_I3(x, x, x, x);
case INDEX_op_cmpsel_vec: case INDEX_op_cmpsel_vec:
return C_O1_I4(x, x, x, x, x); return C_O1_I4(x, x, x, xO, x);
default: default:
g_assert_not_reached(); g_assert_not_reached();