tcg-arm: Implement muls2_i32
We even had the encoding of smull already handy... Cc: Andrzej Zaborowski <balrogg@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -1647,6 +1647,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_mulu2_i32:
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tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
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break;
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case INDEX_op_muls2_i32:
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tcg_out_smull32(s, COND_AL, args[0], args[1], args[2], args[3]);
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break;
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/* XXX: Perhaps args[2] & 0x1f is wrong */
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case INDEX_op_shl_i32:
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c = const_args[2] ?
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@ -1798,6 +1801,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_sub_i32, { "r", "r", "rI" } },
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_muls2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "rI" } },
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{ INDEX_op_andc_i32, { "r", "r", "rI" } },
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{ INDEX_op_or_i32, { "r", "r", "rI" } },
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@ -75,7 +75,7 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_muls2_i32 0
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#define TCG_TARGET_HAS_muls2_i32 1
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enum {
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TCG_AREG0 = TCG_REG_R6,
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