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tcg-i386: Implement multiword arithmetic ops 

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2013-02-19 23:51:57 -08:00 committed by Blue Swirl
parent f6953a7399
commit 624988a53b
2 changed files with 26 additions and 17 deletions
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33
tcg/i386/tcg-target.c
View File

@ -1922,31 +1922,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args, 3);
break;
case INDEX_op_mulu2_i32:
tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
OP_32_64(mulu2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_MUL, args[3]);
break;
case INDEX_op_add2_i32:
OP_32_64(muls2):
tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_IMUL, args[3]);
break;
OP_32_64(add2):
if (const_args[4]) {
tgen_arithi(s, ARITH_ADD, args[0], args[4], 1);
tgen_arithi(s, ARITH_ADD + rexw, args[0], args[4], 1);
} else {
tgen_arithr(s, ARITH_ADD, args[0], args[4]);
tgen_arithr(s, ARITH_ADD + rexw, args[0], args[4]);
}
if (const_args[5]) {
tgen_arithi(s, ARITH_ADC, args[1], args[5], 1);
tgen_arithi(s, ARITH_ADC + rexw, args[1], args[5], 1);
} else {
tgen_arithr(s, ARITH_ADC, args[1], args[5]);
tgen_arithr(s, ARITH_ADC + rexw, args[1], args[5]);
}
break;
case INDEX_op_sub2_i32:
OP_32_64(sub2):
if (const_args[4]) {
tgen_arithi(s, ARITH_SUB, args[0], args[4], 1);
tgen_arithi(s, ARITH_SUB + rexw, args[0], args[4], 1);
} else {
tgen_arithr(s, ARITH_SUB, args[0], args[4]);
tgen_arithr(s, ARITH_SUB + rexw, args[0], args[4]);
}
if (const_args[5]) {
tgen_arithi(s, ARITH_SBB, args[1], args[5], 1);
tgen_arithi(s, ARITH_SBB + rexw, args[1], args[5], 1);
} else {
tgen_arithr(s, ARITH_SBB, args[1], args[5]);
tgen_arithr(s, ARITH_SBB + rexw, args[1], args[5]);
}
break;
@ -2080,6 +2083,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
#endif
{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
{ INDEX_op_muls2_i32, { "a", "d", "a", "r" } },
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
@ -2134,6 +2138,11 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_deposit_i64, { "Q", "0", "Q" } },
{ INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } },
{ INDEX_op_mulu2_i64, { "a", "d", "a", "r" } },
{ INDEX_op_muls2_i64, { "a", "d", "a", "r" } },
{ INDEX_op_add2_i64, { "r", "r", "0", "1", "re", "re" } },
{ INDEX_op_sub2_i64, { "r", "r", "0", "1", "re", "re" } },
#endif
#if TCG_TARGET_REG_BITS == 64

10
tcg/i386/tcg-target.h
View File

@ -95,7 +95,7 @@ typedef enum {
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muls2_i32 1
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_div2_i64 1
@ -118,10 +118,10 @@ typedef enum {
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 1
#endif
#define TCG_TARGET_deposit_i32_valid(ofs, len) \