tcg/i386: Improve TSTNE/TESTEQ vs powers of two
Use "test x,x" when the bit is one of the 4 sign bits. Use "bt imm,x" otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -20,7 +20,7 @@ C_O0_I2(L, L)
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C_O0_I2(qi, r)
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C_O0_I2(re, r)
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C_O0_I2(ri, r)
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C_O0_I2(r, re)
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C_O0_I2(r, reT)
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C_O0_I2(s, L)
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C_O0_I2(x, r)
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C_O0_I3(L, L, L)
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@ -34,7 +34,7 @@ C_O1_I1(r, r)
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C_O1_I1(x, r)
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C_O1_I1(x, x)
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C_O1_I2(q, 0, qi)
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C_O1_I2(q, r, re)
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C_O1_I2(q, r, reT)
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C_O1_I2(r, 0, ci)
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C_O1_I2(r, 0, r)
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C_O1_I2(r, 0, re)
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@ -50,7 +50,7 @@ C_N1_I2(r, r, r)
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C_N1_I2(r, r, rW)
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C_O1_I3(x, 0, x, x)
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C_O1_I3(x, x, x, x)
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C_O1_I4(r, r, re, r, 0)
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C_O1_I4(r, r, reT, r, 0)
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C_O1_I4(r, r, r, ri, ri)
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C_O2_I1(r, r, L)
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C_O2_I2(a, d, a, r)
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@ -28,5 +28,6 @@ REGS('s', ALL_BYTEL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_st8_i32 data */
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*/
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CONST('e', TCG_CT_CONST_S32)
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CONST('I', TCG_CT_CONST_I32)
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CONST('T', TCG_CT_CONST_TST)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('Z', TCG_CT_CONST_U32)
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@ -132,6 +132,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
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#define TCG_CT_CONST_U32 0x200
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#define TCG_CT_CONST_I32 0x400
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#define TCG_CT_CONST_WSZ 0x800
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#define TCG_CT_CONST_TST 0x1000
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/* Registers used with L constraint, which are the first argument
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registers on x86_64, and two random call clobbered registers on
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@ -202,7 +203,8 @@ static bool tcg_target_const_match(int64_t val, int ct,
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return 1;
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}
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if (type == TCG_TYPE_I32) {
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if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 | TCG_CT_CONST_I32)) {
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if (ct & (TCG_CT_CONST_S32 | TCG_CT_CONST_U32 |
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TCG_CT_CONST_I32 | TCG_CT_CONST_TST)) {
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return 1;
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}
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} else {
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@ -215,6 +217,17 @@ static bool tcg_target_const_match(int64_t val, int ct,
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if ((ct & TCG_CT_CONST_I32) && ~val == (int32_t)~val) {
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return 1;
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}
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/*
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* This will be used in combination with TCG_CT_CONST_S32,
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* so "normal" TESTQ is already matched. Also accept:
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* TESTQ -> TESTL (uint32_t)
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* TESTQ -> BT (is_power_of_2)
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*/
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if ((ct & TCG_CT_CONST_TST)
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&& is_tst_cond(cond)
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&& (val == (uint32_t)val || is_power_of_2(val))) {
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return 1;
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}
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}
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if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
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return 1;
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@ -396,6 +409,7 @@ static bool tcg_target_const_match(int64_t val, int ct,
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#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
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#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
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#define OPC_SHRD_Ib (0xac | P_EXT)
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#define OPC_TESTB (0x84)
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#define OPC_TESTL (0x85)
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#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
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#define OPC_UD2 (0x0b | P_EXT)
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@ -442,6 +456,12 @@ static bool tcg_target_const_match(int64_t val, int ct,
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#define OPC_GRP3_Ev (0xf7)
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#define OPC_GRP5 (0xff)
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#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
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#define OPC_GRPBT (0xba | P_EXT)
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#define OPC_GRPBT_BT 4
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#define OPC_GRPBT_BTS 5
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#define OPC_GRPBT_BTR 6
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#define OPC_GRPBT_BTC 7
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/* Group 1 opcode extensions for 0x80-0x83.
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These are also used as modifiers for OPC_ARITH. */
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@ -1454,7 +1474,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small)
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static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1,
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TCGArg arg2, int const_arg2, int rexw)
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{
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int jz;
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int jz, js;
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if (!is_tst_cond(cond)) {
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if (!const_arg2) {
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@ -1469,6 +1489,7 @@ static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1,
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}
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jz = tcg_cond_to_jcc[cond];
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js = (cond == TCG_COND_TSTNE ? JCC_JS : JCC_JNS);
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if (!const_arg2) {
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tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg2);
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@ -1476,17 +1497,40 @@ static int tcg_out_cmp(TCGContext *s, TCGCond cond, TCGArg arg1,
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}
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if (arg2 <= 0xff && (TCG_TARGET_REG_BITS == 64 || arg1 < 4)) {
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if (arg2 == 0x80) {
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tcg_out_modrm(s, OPC_TESTB | P_REXB_R, arg1, arg1);
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return js;
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}
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tcg_out_modrm(s, OPC_GRP3_Eb | P_REXB_RM, EXT3_TESTi, arg1);
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tcg_out8(s, arg2);
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return jz;
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}
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if ((arg2 & ~0xff00) == 0 && arg1 < 4) {
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if (arg2 == 0x8000) {
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tcg_out_modrm(s, OPC_TESTB, arg1 + 4, arg1 + 4);
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return js;
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}
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tcg_out_modrm(s, OPC_GRP3_Eb, EXT3_TESTi, arg1 + 4);
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tcg_out8(s, arg2 >> 8);
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return jz;
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}
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if (is_power_of_2(rexw ? arg2 : (uint32_t)arg2)) {
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int jc = (cond == TCG_COND_TSTNE ? JCC_JB : JCC_JAE);
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int sh = ctz64(arg2);
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rexw = (sh & 32 ? P_REXW : 0);
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if ((sh & 31) == 31) {
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tcg_out_modrm(s, OPC_TESTL | rexw, arg1, arg1);
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return js;
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} else {
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tcg_out_modrm(s, OPC_GRPBT | rexw, OPC_GRPBT_BT, arg1);
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tcg_out8(s, sh);
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return jc;
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}
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}
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if (rexw) {
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if (arg2 == (uint32_t)arg2) {
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rexw = 0;
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@ -3399,7 +3443,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_brcond_i32:
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case INDEX_op_brcond_i64:
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return C_O0_I2(r, re);
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return C_O0_I2(r, reT);
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap16_i64:
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@ -3447,11 +3491,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
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case INDEX_op_setcond_i64:
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case INDEX_op_negsetcond_i32:
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case INDEX_op_negsetcond_i64:
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return C_O1_I2(q, r, re);
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return C_O1_I2(q, r, reT);
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case INDEX_op_movcond_i32:
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case INDEX_op_movcond_i64:
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return C_O1_I4(r, r, re, r, 0);
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return C_O1_I4(r, r, reT, r, 0);
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case INDEX_op_div2_i32:
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case INDEX_op_div2_i64:
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