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hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check

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'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.

'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.

Reported by Coverity via a "DEADCODE" ticket.

Resolves: Coverity CID 1564781
Fixes: 0c54acb824 ("hw/riscv: add RISC-V IOMMU base emulation")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104123839.533442-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2024-11-04 09:38:39 -03:00 committed by Alistair Francis
parent cd5d265f42
commit d3b96a5319
1 changed files with 1 additions and 1 deletions
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hw/riscv/riscv-iommu.c
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@ -820,7 +820,7 @@ static bool riscv_iommu_validate_process_ctx(RISCVIOMMUState *s,
} }
if (ctx->tc & RISCV_IOMMU_DC_TC_SXL) { if (ctx->tc & RISCV_IOMMU_DC_TC_SXL) {
if (mode == RISCV_IOMMU_CAP_SV32 && if (mode == RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 &&
!(s->cap & RISCV_IOMMU_CAP_SV32)) { !(s->cap & RISCV_IOMMU_CAP_SV32)) {
return false; return false;
} }