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hw/riscv/iommu: fix build error with clang

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Introduced in 0c54acb824, "hw/riscv: add RISC-V IOMMU base emulation".

../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64'

  187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext)

      |                 ^

D:/a/_temp/msys64/clang64/lib/clang/18/include/bmi2intrin.h:217:1: note: previous definition is here

  217 | _pext_u64(unsigned long long __X, unsigned long long __Y)

      | ^

After a conversation on the mailing list, it was decided to rename and
add a comment for this function.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241104222225.1523751-1-pierrick.bouvier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Pierrick Bouvier 2024-11-04 14:22:25 -08:00 committed by Philippe Mathieu-Daudé
parent 887c510daa
commit d37eede7a8
1 changed files with 20 additions and 3 deletions
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23
hw/riscv/riscv-iommu.c
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@ -183,8 +183,25 @@ static void riscv_iommu_pri(RISCVIOMMUState *s,
}
}
/* Portable implementation of pext_u64, bit-mask extraction. */
static uint64_t _pext_u64(uint64_t val, uint64_t ext)
/*
* Discards all bits from 'val' whose matching bits in the same
* positions in the mask 'ext' are zeros, and packs the remaining
* bits from 'val' contiguously at the least-significant end of the
* result, keeping the same bit order as 'val' and filling any
* other bits at the most-significant end of the result with zeros.
*
* For example, for the following 'val' and 'ext', the return 'ret'
* will be:
*
* val = a b c d e f g h
* ext = 1 0 1 0 0 1 1 0
* ret = 0 0 0 0 a c f g
*
* This function, taken from the riscv-iommu 1.0 spec, section 2.3.3
* "Process to translate addresses of MSIs", is similar to bit manip
* function PEXT (Parallel bits extract) from x86.
*/
static uint64_t riscv_iommu_pext_u64(uint64_t val, uint64_t ext)
{
uint64_t ret = 0;
uint64_t rot = 1;
@ -528,7 +545,7 @@ static MemTxResult riscv_iommu_msi_write(RISCVIOMMUState *s,
int cause;
/* Interrupt File Number */
intn = _pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
intn = riscv_iommu_pext_u64(PPN_DOWN(gpa), ctx->msi_addr_mask);
if (intn >= 256) {
/* Interrupt file number out of range */
res = MEMTX_ACCESS_ERROR;