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pl011: fix UARTRSR accesses corrupting the UARTCR value

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Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.

Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rob Herring 2014-03-18 13:18:40 -05:00 committed by Peter Maydell
parent 22709e90a2
commit ce8f0905a5
1 changed files with 10 additions and 7 deletions
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17
hw/char/pl011.c
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@ -20,6 +20,7 @@ typedef struct PL011State {
uint32_t readbuff; uint32_t readbuff;
uint32_t flags; uint32_t flags;
uint32_t lcr; uint32_t lcr;
uint32_t rsr;
uint32_t cr; uint32_t cr;
uint32_t dmacr; uint32_t dmacr;
uint32_t int_enabled; uint32_t int_enabled;
@ -81,13 +82,14 @@ static uint64_t pl011_read(void *opaque, hwaddr offset,
} }
if (s->read_count == s->read_trigger - 1) if (s->read_count == s->read_trigger - 1)
s->int_level &= ~ PL011_INT_RX; s->int_level &= ~ PL011_INT_RX;
s->rsr = c >> 8;
pl011_update(s); pl011_update(s);
if (s->chr) { if (s->chr) {
qemu_chr_accept_input(s->chr); qemu_chr_accept_input(s->chr);
} }
return c; return c;
case 1: /* UARTCR */ case 1: /* UARTRSR */
return 0; return s->rsr;
case 6: /* UARTFR */ case 6: /* UARTFR */
return s->flags; return s->flags;
case 8: /* UARTILPR */ case 8: /* UARTILPR */
@ -146,8 +148,8 @@ static void pl011_write(void *opaque, hwaddr offset,
s->int_level |= PL011_INT_TX; s->int_level |= PL011_INT_TX;
pl011_update(s); pl011_update(s);
break; break;
case 1: /* UARTCR */ case 1: /* UARTRSR/UARTECR */
s->cr = value; s->rsr = 0;
break; break;
case 6: /* UARTFR */ case 6: /* UARTFR */
/* Writes to Flag register are ignored. */ /* Writes to Flag register are ignored. */
@ -247,13 +249,14 @@ static const MemoryRegionOps pl011_ops = {
static const VMStateDescription vmstate_pl011 = { static const VMStateDescription vmstate_pl011 = {
.name = "pl011", .name = "pl011",
.version_id = 1, .version_id = 2,
.minimum_version_id = 1, .minimum_version_id = 2,
.minimum_version_id_old = 1, .minimum_version_id_old = 2,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT32(readbuff, PL011State), VMSTATE_UINT32(readbuff, PL011State),
VMSTATE_UINT32(flags, PL011State), VMSTATE_UINT32(flags, PL011State),
VMSTATE_UINT32(lcr, PL011State), VMSTATE_UINT32(lcr, PL011State),
VMSTATE_UINT32(rsr, PL011State),
VMSTATE_UINT32(cr, PL011State), VMSTATE_UINT32(cr, PL011State),
VMSTATE_UINT32(dmacr, PL011State), VMSTATE_UINT32(dmacr, PL011State),
VMSTATE_UINT32(int_enabled, PL011State), VMSTATE_UINT32(int_enabled, PL011State),