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target/ppc: Implement LDBAR, TTR SPRs

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LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-05-22 16:23:21 +10:00
parent 4d2b0ad32a
commit c9d5aedf40
2 changed files with 12 additions and 0 deletions
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2
target/ppc/cpu.h
View File

@ -2098,6 +2098,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_DEXCR (0x33C) #define SPR_DEXCR (0x33C)
#define SPR_IC (0x350) #define SPR_IC (0x350)
#define SPR_VTB (0x351) #define SPR_VTB (0x351)
#define SPR_LDBAR (0x352)
#define SPR_MMCRC (0x353) #define SPR_MMCRC (0x353)
#define SPR_PSSCR (0x357) #define SPR_PSSCR (0x357)
#define SPR_440_INV0 (0x370) #define SPR_440_INV0 (0x370)
@ -2144,6 +2145,7 @@ void ppc_compat_add_property(Object *obj, const char *name,
#define SPR_440_IVLIM (0x399) #define SPR_440_IVLIM (0x399)
#define SPR_TSCR (0x399) #define SPR_TSCR (0x399)
#define SPR_750_DMAU (0x39A) #define SPR_750_DMAU (0x39A)
#define SPR_POWER_TTR (0x39A)
#define SPR_750_DMAL (0x39B) #define SPR_750_DMAL (0x39B)
#define SPR_440_RSTCFG (0x39B) #define SPR_440_RSTCFG (0x39B)
#define SPR_BOOKE_DCDBTRL (0x39C) #define SPR_BOOKE_DCDBTRL (0x39C)

10
target/ppc/cpu_init.c
View File

@ -5767,6 +5767,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env)
&spr_access_nop, &spr_write_generic, &spr_access_nop, &spr_write_generic,
&spr_access_nop, &spr_write_generic, &spr_access_nop, &spr_write_generic,
0x00000000); 0x00000000);
spr_register_hv(env, SPR_LDBAR, "LDBAR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_core_lpar_write_generic,
0x00000000);
spr_register_hv(env, SPR_POWER_TTR, "TTR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_core_write_generic,
0x00000000);
#endif #endif
} }