target/ppc: Add SMT support to PTCR SPR
PTCR is a per-core register. Reviewed-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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@ -173,6 +173,7 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
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void helper_store_ptcr(CPUPPCState *env, target_ulong val)
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{
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if (env->spr[SPR_PTCR] != val) {
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CPUState *cs = env_cpu(env);
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PowerPCCPU *cpu = env_archcpu(env);
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target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
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target_ulong patbsize = val & PTCR_PATS;
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@ -194,8 +195,19 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val)
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return;
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}
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env->spr[SPR_PTCR] = val;
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tlb_flush(env_cpu(env));
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if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
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env->spr[SPR_PTCR] = val;
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tlb_flush(cs);
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} else {
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CPUState *ccs;
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THREAD_SIBLING_FOREACH(cs, ccs) {
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PowerPCCPU *ccpu = POWERPC_CPU(ccs);
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CPUPPCState *cenv = &ccpu->env;
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cenv->spr[SPR_PTCR] = val;
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tlb_flush(ccs);
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}
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}
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}
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}
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@ -909,6 +909,10 @@ void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
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}
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void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
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{
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if (!gen_serialize_core(ctx)) {
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return;
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}
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gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]);
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}
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