aspeed/smc: Add support for DMAs
The FMC controller on the Aspeed SoCs support DMA to access the flash modules. It can operate in a normal mode, to copy to or from the flash module mapping window, or in a checksum calculation mode, to evaluate the best clock settings for reads. The model introduces two custom address spaces for DMAs: one for the AHB window of the FMC flash devices and one for the DRAM. The latter is populated using a "dram" link set from the machine with the RAM container region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Joel Stanley <joel@jms.id.au> Message-id: 20190904070506.1052-6-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -190,6 +190,8 @@ static void aspeed_board_init(MachineState *machine,
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&error_abort);
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object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus",
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&error_abort);
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object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container),
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"dram", &error_abort);
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if (machine->kernel_filename) {
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/*
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* When booting with a -kernel command line there is no u-boot
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@ -191,6 +191,8 @@ static void aspeed_soc_init(Object *obj)
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typename);
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object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
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&error_abort);
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object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram",
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&error_abort);
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for (i = 0; i < sc->info->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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@ -28,6 +28,8 @@
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "exec/address-spaces.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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@ -112,8 +114,8 @@
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#define DMA_CTRL_FREQ_SHIFT 4
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#define DMA_CTRL_MODE (1 << 3)
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#define DMA_CTRL_CKSUM (1 << 2)
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#define DMA_CTRL_DIR (1 << 1)
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#define DMA_CTRL_EN (1 << 0)
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#define DMA_CTRL_WRITE (1 << 1)
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#define DMA_CTRL_ENABLE (1 << 0)
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/* DMA Flash Side Address */
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#define R_DMA_FLASH_ADDR (0x84 / 4)
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@ -145,6 +147,24 @@
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#define ASPEED_SOC_SPI_FLASH_BASE 0x30000000
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#define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000
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/*
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* DMA DRAM addresses should be 4 bytes aligned and the valid address
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* range is 0x40000000 - 0x5FFFFFFF (AST2400)
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* 0x80000000 - 0xBFFFFFFF (AST2500)
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*
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* DMA flash addresses should be 4 bytes aligned and the valid address
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* range is 0x20000000 - 0x2FFFFFFF.
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*
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* DMA length is from 4 bytes to 32MB
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* 0: 4 bytes
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* 0x7FFFFF: 32M bytes
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*/
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#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \
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((val) & (s)->ctrl->dma_dram_mask))
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#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \
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((val) & (s)->ctrl->dma_flash_mask))
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#define DMA_LENGTH(val) ((val) & 0x01FFFFFC)
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/* Flash opcodes. */
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#define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */
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@ -214,6 +234,8 @@ static const AspeedSMCController controllers[] = {
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.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
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.flash_window_size = 0x10000000,
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.has_dma = true,
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.dma_flash_mask = 0x0FFFFFFC,
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.dma_dram_mask = 0x1FFFFFFC,
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.nregs = ASPEED_SMC_R_MAX,
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}, {
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.name = "aspeed.spi1-ast2400",
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@ -240,6 +262,8 @@ static const AspeedSMCController controllers[] = {
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.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
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.flash_window_size = 0x10000000,
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.has_dma = true,
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.dma_flash_mask = 0x0FFFFFFC,
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.dma_dram_mask = 0x3FFFFFFC,
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.nregs = ASPEED_SMC_R_MAX,
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}, {
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.name = "aspeed.spi1-ast2500",
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@ -732,9 +756,6 @@ static void aspeed_smc_reset(DeviceState *d)
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memset(s->regs, 0, sizeof s->regs);
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/* Pretend DMA is done (u-boot initialization) */
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s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS;
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/* Unselect all slaves */
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for (i = 0; i < s->num_cs; ++i) {
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s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE;
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@ -775,6 +796,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
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addr == s->r_ce_ctrl ||
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addr == R_INTR_CTRL ||
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addr == R_DUMMY_DATA ||
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(s->ctrl->has_dma && addr == R_DMA_CTRL) ||
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(s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) ||
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(s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
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(s->ctrl->has_dma && addr == R_DMA_LEN) ||
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(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
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(addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
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(addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
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return s->regs[addr];
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@ -785,6 +811,149 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
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}
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}
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/*
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* Accumulate the result of the reads to provide a checksum that will
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* be used to validate the read timing settings.
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*/
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static void aspeed_smc_dma_checksum(AspeedSMCState *s)
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{
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MemTxResult result;
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uint32_t data;
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if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid direction for DMA checksum\n", __func__);
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return;
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}
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while (s->regs[R_DMA_LEN]) {
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data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
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__func__, s->regs[R_DMA_FLASH_ADDR]);
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return;
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}
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/*
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* When the DMA is on-going, the DMA registers are updated
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* with the current working addresses and length.
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*/
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s->regs[R_DMA_CHECKSUM] += data;
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s->regs[R_DMA_FLASH_ADDR] += 4;
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s->regs[R_DMA_LEN] -= 4;
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}
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}
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static void aspeed_smc_dma_rw(AspeedSMCState *s)
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{
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MemTxResult result;
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uint32_t data;
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while (s->regs[R_DMA_LEN]) {
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if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) {
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data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n",
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__func__, s->regs[R_DMA_DRAM_ADDR]);
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return;
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}
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address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
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data, MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n",
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__func__, s->regs[R_DMA_FLASH_ADDR]);
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return;
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}
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} else {
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data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR],
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MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n",
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__func__, s->regs[R_DMA_FLASH_ADDR]);
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return;
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}
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address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR],
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data, MEMTXATTRS_UNSPECIFIED, &result);
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if (result != MEMTX_OK) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n",
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__func__, s->regs[R_DMA_DRAM_ADDR]);
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return;
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}
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}
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/*
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* When the DMA is on-going, the DMA registers are updated
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* with the current working addresses and length.
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*/
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s->regs[R_DMA_FLASH_ADDR] += 4;
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s->regs[R_DMA_DRAM_ADDR] += 4;
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s->regs[R_DMA_LEN] -= 4;
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}
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}
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static void aspeed_smc_dma_stop(AspeedSMCState *s)
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{
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/*
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* When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the
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* engine is idle
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*/
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s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS;
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s->regs[R_DMA_CHECKSUM] = 0;
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/*
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* Lower the DMA irq in any case. The IRQ control register could
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* have been cleared before disabling the DMA.
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*/
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qemu_irq_lower(s->irq);
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}
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/*
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* When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA
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* can start even if the result of the previous was not collected.
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*/
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static bool aspeed_smc_dma_in_progress(AspeedSMCState *s)
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{
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return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE &&
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!(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS);
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}
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static void aspeed_smc_dma_done(AspeedSMCState *s)
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{
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s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS;
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if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) {
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qemu_irq_raise(s->irq);
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}
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}
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static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl)
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{
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if (!(dma_ctrl & DMA_CTRL_ENABLE)) {
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s->regs[R_DMA_CTRL] = dma_ctrl;
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aspeed_smc_dma_stop(s);
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return;
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}
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if (aspeed_smc_dma_in_progress(s)) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__);
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return;
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}
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s->regs[R_DMA_CTRL] = dma_ctrl;
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if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) {
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aspeed_smc_dma_checksum(s);
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} else {
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aspeed_smc_dma_rw(s);
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}
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aspeed_smc_dma_done(s);
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}
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static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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@ -810,6 +979,16 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
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}
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} else if (addr == R_DUMMY_DATA) {
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s->regs[addr] = value & 0xff;
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} else if (addr == R_INTR_CTRL) {
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s->regs[addr] = value;
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} else if (s->ctrl->has_dma && addr == R_DMA_CTRL) {
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aspeed_smc_dma_ctrl(s, value);
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} else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) {
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s->regs[addr] = DMA_DRAM_ADDR(s, value);
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} else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) {
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s->regs[addr] = DMA_FLASH_ADDR(s, value);
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} else if (s->ctrl->has_dma && addr == R_DMA_LEN) {
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s->regs[addr] = DMA_LENGTH(value);
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} else {
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qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n",
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__func__, addr);
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@ -824,6 +1003,28 @@ static const MemoryRegionOps aspeed_smc_ops = {
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.valid.unaligned = true,
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};
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/*
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* Initialize the custom address spaces for DMAs
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*/
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static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp)
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{
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char *name;
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if (!s->dram_mr) {
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error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set");
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return;
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}
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name = g_strdup_printf("%s-dma-flash", s->ctrl->name);
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address_space_init(&s->flash_as, &s->mmio_flash, name);
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g_free(name);
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name = g_strdup_printf("%s-dma-dram", s->ctrl->name);
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address_space_init(&s->dram_as, s->dram_mr, name);
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g_free(name);
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}
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static void aspeed_smc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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@ -849,10 +1050,12 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
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s->num_cs = s->ctrl->max_slaves;
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}
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/* DMA irq. Keep it first for the initialization in the SoC */
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sysbus_init_irq(sbd, &s->irq);
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s->spi = ssi_create_bus(dev, "spi");
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/* Setup cs_lines for slaves */
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sysbus_init_irq(sbd, &s->irq);
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s->cs_lines = g_new0(qemu_irq, s->num_cs);
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ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
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@ -899,6 +1102,11 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
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memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio);
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offset += fl->size;
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}
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/* DMA support */
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if (s->ctrl->has_dma) {
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aspeed_smc_dma_setup(s, errp);
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}
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}
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static const VMStateDescription vmstate_aspeed_smc = {
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@ -916,6 +1124,8 @@ static const VMStateDescription vmstate_aspeed_smc = {
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static Property aspeed_smc_properties[] = {
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DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1),
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DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0),
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DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
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TYPE_MEMORY_REGION, MemoryRegion *),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -46,6 +46,8 @@ typedef struct AspeedSMCController {
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hwaddr flash_window_base;
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uint32_t flash_window_size;
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bool has_dma;
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hwaddr dma_flash_mask;
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hwaddr dma_dram_mask;
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uint32_t nregs;
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} AspeedSMCController;
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@ -101,6 +103,10 @@ typedef struct AspeedSMCState {
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/* for DMA support */
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uint64_t sdram_base;
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AddressSpace flash_as;
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MemoryRegion *dram_mr;
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AddressSpace dram_as;
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AspeedSMCFlash *flashes;
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uint8_t snoop_index;
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