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target/riscv: debug: Check VU/VS modes for type 2 trigger

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Type 2 trigger cannot be fired in VU/VS modes.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220909134215.1843865-8-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-09-09 21:42:14 +08:00 committed by Alistair Francis
parent d1c111411e
commit c32461d8ee
1 changed files with 10 additions and 0 deletions
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10
target/riscv/debug.c
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@ -464,6 +464,11 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
switch (trigger_type) { switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH: case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
if (riscv_cpu_virt_enabled(env)) {
return false;
}
ctrl = env->tdata1[i]; ctrl = env->tdata1[i];
pc = env->tdata2[i]; pc = env->tdata2[i];
@ -499,6 +504,11 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
switch (trigger_type) { switch (trigger_type) {
case TRIGGER_TYPE_AD_MATCH: case TRIGGER_TYPE_AD_MATCH:
/* type 2 trigger cannot be fired in VU/VS mode */
if (riscv_cpu_virt_enabled(env)) {
return false;
}
ctrl = env->tdata1[i]; ctrl = env->tdata1[i];
addr = env->tdata2[i]; addr = env->tdata2[i];
flags = 0; flags = 0;