mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/loongarch: Implement vneg

Browse Source 
This patch includes;
- VNEG.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-7-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:32 +08:00
parent d8be64c1c5
commit be9ec55758
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
3 changed files with 37 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
target/loongarch/disas.c
View File

@ -802,6 +802,11 @@ static void output_vv_i(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm); output(ctx, mnemonic, "v%d, v%d, 0x%x", a->vd, a->vj, a->imm);
} }
static void output_vv(DisasContext *ctx, arg_vv *a, const char *mnemonic)
{
output(ctx, mnemonic, "v%d, v%d", a->vd, a->vj);
}
INSN_LSX(vadd_b, vvv) INSN_LSX(vadd_b, vvv)
INSN_LSX(vadd_h, vvv) INSN_LSX(vadd_h, vvv)
INSN_LSX(vadd_w, vvv) INSN_LSX(vadd_w, vvv)
@ -821,3 +826,8 @@ INSN_LSX(vsubi_bu, vv_i)
INSN_LSX(vsubi_hu, vv_i) INSN_LSX(vsubi_hu, vv_i)
INSN_LSX(vsubi_wu, vv_i) INSN_LSX(vsubi_wu, vv_i)
INSN_LSX(vsubi_du, vv_i) INSN_LSX(vsubi_du, vv_i)
INSN_LSX(vneg_b, vv)
INSN_LSX(vneg_h, vv)
INSN_LSX(vneg_w, vv)
INSN_LSX(vneg_d, vv)

20
target/loongarch/insn_trans/trans_lsx.c.inc
View File

@ -44,6 +44,21 @@ static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
return true; return true;
} }
static bool gvec_vv(DisasContext *ctx, arg_vv *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t))
{
uint32_t vd_ofs, vj_ofs;
CHECK_SXE;
vd_ofs = vec_full_offset(a->vd);
vj_ofs = vec_full_offset(a->vj);
func(mop, vd_ofs, vj_ofs, 16, ctx->vl/8);
return true;
}
static bool gvec_vv_i(DisasContext *ctx, arg_vv_i *a, MemOp mop, static bool gvec_vv_i(DisasContext *ctx, arg_vv_i *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t, void (*func)(unsigned, uint32_t, uint32_t,
int64_t, uint32_t, uint32_t)) int64_t, uint32_t, uint32_t))
@ -120,3 +135,8 @@ TRANS(vsubi_bu, gvec_subi, MO_8)
TRANS(vsubi_hu, gvec_subi, MO_16) TRANS(vsubi_hu, gvec_subi, MO_16)
TRANS(vsubi_wu, gvec_subi, MO_32) TRANS(vsubi_wu, gvec_subi, MO_32)
TRANS(vsubi_du, gvec_subi, MO_64) TRANS(vsubi_du, gvec_subi, MO_64)
TRANS(vneg_b, gvec_vv, MO_8, tcg_gen_gvec_neg)
TRANS(vneg_h, gvec_vv, MO_16, tcg_gen_gvec_neg)
TRANS(vneg_w, gvec_vv, MO_32, tcg_gen_gvec_neg)
TRANS(vneg_d, gvec_vv, MO_64, tcg_gen_gvec_neg)

7
target/loongarch/insns.decode
View File

@ -490,12 +490,14 @@ dbcl 0000 00000010 10101 ............... @i15
# LSX Argument sets # LSX Argument sets
# #
&vv vd vj
&vvv vd vj vk &vvv vd vj vk
&vv_i vd vj imm &vv_i vd vj imm
# #
# LSX Formats # LSX Formats
# #
@vv .... ........ ..... ..... vj:5 vd:5 &vv
@vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv @vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv
@vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i @vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i
@ -518,3 +520,8 @@ vsubi_bu 0111 00101000 11000 ..... ..... ..... @vv_ui5
vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5 vsubi_hu 0111 00101000 11001 ..... ..... ..... @vv_ui5
vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5 vsubi_wu 0111 00101000 11010 ..... ..... ..... @vv_ui5
vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5 vsubi_du 0111 00101000 11011 ..... ..... ..... @vv_ui5
vneg_b 0111 00101001 11000 01100 ..... ..... @vv
vneg_h 0111 00101001 11000 01101 ..... ..... @vv
vneg_w 0111 00101001 11000 01110 ..... ..... @vv
vneg_d 0111 00101001 11000 01111 ..... ..... @vv