mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

target/mips: Replace CP0_Config0 magic values by proper definitions

Browse Source 
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-3-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-01 12:41:39 +01:00
parent 8cd0b410a2
commit b4cbbb47b0
1 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
target/mips/translate_init.c.inc
View File

@ -495,7 +495,8 @@ const mips_def_t mips_defs[] =
.name = "R4000",
.CP0_PRid = 0x00000400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
.CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
(2 << CP0C0_K0),
/* Note: Config1 is only used internally, the R4000 has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
@ -516,7 +517,8 @@ const mips_def_t mips_defs[] =
.name = "VR5432",
.CP0_PRid = 0x00005400,
/* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
.CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
.CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) |
(2 << CP0C0_K0),
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
.CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
.CP0_LLAddr_shift = 4,
@ -766,8 +768,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2E",
.CP0_PRid = 0x6302,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
(0x1<<5) | (0x1<<4) | (0x1<<1),
.CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
(1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2E has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
@ -786,8 +788,8 @@ const mips_def_t mips_defs[] =
.name = "Loongson-2F",
.CP0_PRid = 0x6303,
/* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
.CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
(0x1<<5) | (0x1<<4) | (0x1<<1),
.CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) |
(1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0),
/* Note: Config1 is only used internally,
Loongson-2F has only Config0. */
.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),