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target/mips: Add CP0 Config0 register definitions for MIPS3 ISA

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The MIPS3 and MIPS32/64 ISA use different definitions
for the CP0 Config0 register.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201201132817.2863301-2-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-01 12:29:22 +01:00
parent 7c79721606
commit 8cd0b410a2
1 changed files with 9 additions and 1 deletions
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10
target/mips/cpu.h
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@ -828,7 +828,7 @@ struct CPUMIPSState {
#define CP0EBase_WG 11
target_ulong CP0_CMGCRBase;
/*
* CP0 Register 16
* CP0 Register 16 (after Release 1)
*/
int32_t CP0_Config0;
#define CP0C0_M 31
@ -845,6 +845,14 @@ struct CPUMIPSState {
#define CP0C0_VI 3
#define CP0C0_K0 0 /* 2..0 */
#define CP0C0_AR_LENGTH 3
/*
* CP0 Register 16 (before Release 1)
*/
#define CP0C0_Impl 16 /* 24..16 */
#define CP0C0_IC 9 /* 11..9 */
#define CP0C0_DC 6 /* 8..6 */
#define CP0C0_IB 5
#define CP0C0_DB 4
int32_t CP0_Config1;
#define CP0C1_M 31
#define CP0C1_MMU 25 /* 30..25 */