Sparc: split helper.c
Move CPU init to cpu_init.c and interrupt handling to int32_helper.c for Sparc32 and int64_helper.c for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
c65f6fd4bc
commit
ab3b491f21
@ -76,6 +76,11 @@ libobj-y += cpuid.o
|
||||
endif
|
||||
libobj-$(CONFIG_NEED_MMU) += mmu.o
|
||||
libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
|
||||
ifeq ($(TARGET_BASE_ARCH), sparc)
|
||||
libobj-y += cpu_init.o
|
||||
endif
|
||||
libobj-$(TARGET_SPARC) += int32_helper.o
|
||||
libobj-$(TARGET_SPARC64) += int64_helper.o
|
||||
|
||||
libobj-y += disas.o
|
||||
|
||||
|
||||
@ -485,10 +485,11 @@ typedef struct CPUSPARCState {
|
||||
} CPUSPARCState;
|
||||
|
||||
#ifndef NO_CPU_IO_DEFS
|
||||
/* helper.c */
|
||||
/* cpu_init.c */
|
||||
CPUSPARCState *cpu_sparc_init(const char *cpu_model);
|
||||
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
|
||||
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
|
||||
/* helper.c */
|
||||
int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
|
||||
int mmu_idx);
|
||||
#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
|
||||
|
||||
848
target-sparc/cpu_init.c
Normal file
848
target-sparc/cpu_init.c
Normal file
@ -0,0 +1,848 @@
|
||||
/*
|
||||
* Sparc CPU init helpers
|
||||
*
|
||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
//#define DEBUG_FEATURES
|
||||
|
||||
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model);
|
||||
|
||||
void cpu_reset(CPUSPARCState *env)
|
||||
{
|
||||
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
||||
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
||||
log_cpu_state(env, 0);
|
||||
}
|
||||
|
||||
tlb_flush(env, 1);
|
||||
env->cwp = 0;
|
||||
#ifndef TARGET_SPARC64
|
||||
env->wim = 1;
|
||||
#endif
|
||||
env->regwptr = env->regbase + (env->cwp * 16);
|
||||
CC_OP = CC_OP_FLAGS;
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
#ifdef TARGET_SPARC64
|
||||
env->cleanwin = env->nwindows - 2;
|
||||
env->cansave = env->nwindows - 2;
|
||||
env->pstate = PS_RMO | PS_PEF | PS_IE;
|
||||
env->asi = 0x82; /* Primary no-fault */
|
||||
#endif
|
||||
#else
|
||||
#if !defined(TARGET_SPARC64)
|
||||
env->psret = 0;
|
||||
env->psrs = 1;
|
||||
env->psrps = 1;
|
||||
#endif
|
||||
#ifdef TARGET_SPARC64
|
||||
env->pstate = PS_PRIV|PS_RED|PS_PEF|PS_AG;
|
||||
env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
|
||||
env->tl = env->maxtl;
|
||||
cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
|
||||
env->lsu = 0;
|
||||
#else
|
||||
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
||||
env->mmuregs[0] |= env->def->mmu_bm;
|
||||
#endif
|
||||
env->pc = 0;
|
||||
env->npc = env->pc + 4;
|
||||
#endif
|
||||
env->cache_control = 0;
|
||||
}
|
||||
|
||||
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
|
||||
{
|
||||
sparc_def_t def1, *def = &def1;
|
||||
|
||||
if (cpu_sparc_find_by_name(def, cpu_model) < 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
env->def = g_malloc0(sizeof(*def));
|
||||
memcpy(env->def, def, sizeof(*def));
|
||||
#if defined(CONFIG_USER_ONLY)
|
||||
if ((env->def->features & CPU_FEATURE_FLOAT)) {
|
||||
env->def->features |= CPU_FEATURE_FLOAT128;
|
||||
}
|
||||
#endif
|
||||
env->cpu_model_str = cpu_model;
|
||||
env->version = def->iu_version;
|
||||
env->fsr = def->fpu_version;
|
||||
env->nwindows = def->nwindows;
|
||||
#if !defined(TARGET_SPARC64)
|
||||
env->mmuregs[0] |= def->mmu_version;
|
||||
cpu_sparc_set_id(env, 0);
|
||||
env->mxccregs[7] |= def->mxcc_version;
|
||||
#else
|
||||
env->mmu_version = def->mmu_version;
|
||||
env->maxtl = def->maxtl;
|
||||
env->version |= def->maxtl << 8;
|
||||
env->version |= def->nwindows - 1;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void cpu_sparc_close(CPUSPARCState *env)
|
||||
{
|
||||
free(env->def);
|
||||
free(env);
|
||||
}
|
||||
|
||||
CPUSPARCState *cpu_sparc_init(const char *cpu_model)
|
||||
{
|
||||
CPUSPARCState *env;
|
||||
|
||||
env = g_malloc0(sizeof(CPUSPARCState));
|
||||
cpu_exec_init(env);
|
||||
|
||||
gen_intermediate_code_init(env);
|
||||
|
||||
if (cpu_sparc_register(env, cpu_model) < 0) {
|
||||
cpu_sparc_close(env);
|
||||
return NULL;
|
||||
}
|
||||
qemu_init_vcpu(env);
|
||||
|
||||
return env;
|
||||
}
|
||||
|
||||
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
|
||||
{
|
||||
#if !defined(TARGET_SPARC64)
|
||||
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
|
||||
#endif
|
||||
}
|
||||
|
||||
static const sparc_def_t sparc_defs[] = {
|
||||
#ifdef TARGET_SPARC64
|
||||
{
|
||||
.name = "Fujitsu Sparc64",
|
||||
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 4,
|
||||
.maxtl = 4,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu Sparc64 III",
|
||||
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 5,
|
||||
.maxtl = 4,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu Sparc64 IV",
|
||||
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu Sparc64 V",
|
||||
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI UltraSparc I",
|
||||
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI UltraSparc II",
|
||||
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI UltraSparc IIi",
|
||||
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI UltraSparc IIe",
|
||||
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc III",
|
||||
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc III Cu",
|
||||
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_3,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc IIIi",
|
||||
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc IV",
|
||||
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_4,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc IV+",
|
||||
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc IIIi+",
|
||||
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_3,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc T1",
|
||||
/* defined in sparc_ifu_fdp.v and ctu.h */
|
||||
.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_sun4v,
|
||||
.nwindows = 8,
|
||||
.maxtl = 6,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
|
||||
| CPU_FEATURE_GL,
|
||||
},
|
||||
{
|
||||
.name = "Sun UltraSparc T2",
|
||||
/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
|
||||
.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_sun4v,
|
||||
.nwindows = 8,
|
||||
.maxtl = 6,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
|
||||
| CPU_FEATURE_GL,
|
||||
},
|
||||
{
|
||||
.name = "NEC UltraSparc I",
|
||||
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
|
||||
.fpu_version = 0x00000000,
|
||||
.mmu_version = mmu_us_12,
|
||||
.nwindows = 8,
|
||||
.maxtl = 5,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
#else
|
||||
{
|
||||
.name = "Fujitsu MB86900",
|
||||
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 7,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu MB86904",
|
||||
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x00ffffc0,
|
||||
.mmu_cxr_mask = 0x000000ff,
|
||||
.mmu_sfsr_mask = 0x00016fff,
|
||||
.mmu_trcr_mask = 0x00ffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Fujitsu MB86907",
|
||||
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x000000ff,
|
||||
.mmu_sfsr_mask = 0x00016fff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "LSI L64811",
|
||||
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
|
||||
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Cypress CY7C601",
|
||||
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Cypress CY7C611",
|
||||
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "TI MicroSparc I",
|
||||
.iu_version = 0x41000000,
|
||||
.fpu_version = 4 << 17,
|
||||
.mmu_version = 0x41000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0x00016fff,
|
||||
.mmu_trcr_mask = 0x0000003f,
|
||||
.nwindows = 7,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
|
||||
CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FMUL,
|
||||
},
|
||||
{
|
||||
.name = "TI MicroSparc II",
|
||||
.iu_version = 0x42000000,
|
||||
.fpu_version = 4 << 17,
|
||||
.mmu_version = 0x02000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x00ffffc0,
|
||||
.mmu_cxr_mask = 0x000000ff,
|
||||
.mmu_sfsr_mask = 0x00016fff,
|
||||
.mmu_trcr_mask = 0x00ffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI MicroSparc IIep",
|
||||
.iu_version = 0x42000000,
|
||||
.fpu_version = 4 << 17,
|
||||
.mmu_version = 0x04000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x00ffffc0,
|
||||
.mmu_cxr_mask = 0x000000ff,
|
||||
.mmu_sfsr_mask = 0x00016bff,
|
||||
.mmu_trcr_mask = 0x00ffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 40", /* STP1020NPGA */
|
||||
.iu_version = 0x41000000, /* SuperSPARC 2.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 50", /* STP1020PGA */
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 51",
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 60", /* STP1020APGA */
|
||||
.iu_version = 0x40000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc 61",
|
||||
.iu_version = 0x44000000, /* SuperSPARC 3.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "TI SuperSparc II",
|
||||
.iu_version = 0x40000000, /* SuperSPARC II 1.x */
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
|
||||
.mmu_bm = 0x00002000,
|
||||
.mmu_ctpr_mask = 0xffffffc0,
|
||||
.mmu_cxr_mask = 0x0000ffff,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.mxcc_version = 0x00000104,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Ross RT625",
|
||||
.iu_version = 0x1e000000,
|
||||
.fpu_version = 1 << 17,
|
||||
.mmu_version = 0x1e000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "Ross RT620",
|
||||
.iu_version = 0x1f000000,
|
||||
.fpu_version = 1 << 17,
|
||||
.mmu_version = 0x1f000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "BIT B5010",
|
||||
.iu_version = 0x20000000,
|
||||
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
|
||||
.mmu_version = 0x20000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Matsushita MN10501",
|
||||
.iu_version = 0x50000000,
|
||||
.fpu_version = 0 << 17,
|
||||
.mmu_version = 0x50000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT |
|
||||
CPU_FEATURE_FSMULD,
|
||||
},
|
||||
{
|
||||
.name = "Weitek W8601",
|
||||
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
|
||||
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
|
||||
.mmu_version = 0x10 << 24,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES,
|
||||
},
|
||||
{
|
||||
.name = "LEON2",
|
||||
.iu_version = 0xf2000000,
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0xf2000000,
|
||||
.mmu_bm = 0x00004000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
|
||||
},
|
||||
{
|
||||
.name = "LEON3",
|
||||
.iu_version = 0xf3000000,
|
||||
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
|
||||
.mmu_version = 0xf3000000,
|
||||
.mmu_bm = 0x00000000,
|
||||
.mmu_ctpr_mask = 0x007ffff0,
|
||||
.mmu_cxr_mask = 0x0000003f,
|
||||
.mmu_sfsr_mask = 0xffffffff,
|
||||
.mmu_trcr_mask = 0xffffffff,
|
||||
.nwindows = 8,
|
||||
.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
|
||||
CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static const char * const feature_name[] = {
|
||||
"float",
|
||||
"float128",
|
||||
"swap",
|
||||
"mul",
|
||||
"div",
|
||||
"flush",
|
||||
"fsqrt",
|
||||
"fmul",
|
||||
"vis1",
|
||||
"vis2",
|
||||
"fsmuld",
|
||||
"hypv",
|
||||
"cmt",
|
||||
"gl",
|
||||
};
|
||||
|
||||
static void print_features(FILE *f, fprintf_function cpu_fprintf,
|
||||
uint32_t features, const char *prefix)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
||||
if (feature_name[i] && (features & (1 << i))) {
|
||||
if (prefix) {
|
||||
(*cpu_fprintf)(f, "%s", prefix);
|
||||
}
|
||||
(*cpu_fprintf)(f, "%s ", feature_name[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
|
||||
if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
||||
*features |= 1 << i;
|
||||
return;
|
||||
}
|
||||
}
|
||||
fprintf(stderr, "CPU feature %s not found\n", flagname);
|
||||
}
|
||||
|
||||
static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model)
|
||||
{
|
||||
unsigned int i;
|
||||
const sparc_def_t *def = NULL;
|
||||
char *s = strdup(cpu_model);
|
||||
char *featurestr, *name = strtok(s, ",");
|
||||
uint32_t plus_features = 0;
|
||||
uint32_t minus_features = 0;
|
||||
uint64_t iu_version;
|
||||
uint32_t fpu_version, mmu_version, nwindows;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
||||
if (strcasecmp(name, sparc_defs[i].name) == 0) {
|
||||
def = &sparc_defs[i];
|
||||
}
|
||||
}
|
||||
if (!def) {
|
||||
goto error;
|
||||
}
|
||||
memcpy(cpu_def, def, sizeof(*def));
|
||||
|
||||
featurestr = strtok(NULL, ",");
|
||||
while (featurestr) {
|
||||
char *val;
|
||||
|
||||
if (featurestr[0] == '+') {
|
||||
add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
||||
} else if (featurestr[0] == '-') {
|
||||
add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
||||
} else if ((val = strchr(featurestr, '='))) {
|
||||
*val = 0; val++;
|
||||
if (!strcmp(featurestr, "iu_version")) {
|
||||
char *err;
|
||||
|
||||
iu_version = strtoll(val, &err, 0);
|
||||
if (!*val || *err) {
|
||||
fprintf(stderr, "bad numerical value %s\n", val);
|
||||
goto error;
|
||||
}
|
||||
cpu_def->iu_version = iu_version;
|
||||
#ifdef DEBUG_FEATURES
|
||||
fprintf(stderr, "iu_version %" PRIx64 "\n", iu_version);
|
||||
#endif
|
||||
} else if (!strcmp(featurestr, "fpu_version")) {
|
||||
char *err;
|
||||
|
||||
fpu_version = strtol(val, &err, 0);
|
||||
if (!*val || *err) {
|
||||
fprintf(stderr, "bad numerical value %s\n", val);
|
||||
goto error;
|
||||
}
|
||||
cpu_def->fpu_version = fpu_version;
|
||||
#ifdef DEBUG_FEATURES
|
||||
fprintf(stderr, "fpu_version %x\n", fpu_version);
|
||||
#endif
|
||||
} else if (!strcmp(featurestr, "mmu_version")) {
|
||||
char *err;
|
||||
|
||||
mmu_version = strtol(val, &err, 0);
|
||||
if (!*val || *err) {
|
||||
fprintf(stderr, "bad numerical value %s\n", val);
|
||||
goto error;
|
||||
}
|
||||
cpu_def->mmu_version = mmu_version;
|
||||
#ifdef DEBUG_FEATURES
|
||||
fprintf(stderr, "mmu_version %x\n", mmu_version);
|
||||
#endif
|
||||
} else if (!strcmp(featurestr, "nwindows")) {
|
||||
char *err;
|
||||
|
||||
nwindows = strtol(val, &err, 0);
|
||||
if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
||||
nwindows < MIN_NWINDOWS) {
|
||||
fprintf(stderr, "bad numerical value %s\n", val);
|
||||
goto error;
|
||||
}
|
||||
cpu_def->nwindows = nwindows;
|
||||
#ifdef DEBUG_FEATURES
|
||||
fprintf(stderr, "nwindows %d\n", nwindows);
|
||||
#endif
|
||||
} else {
|
||||
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
||||
goto error;
|
||||
}
|
||||
} else {
|
||||
fprintf(stderr, "feature string `%s' not in format "
|
||||
"(+feature|-feature|feature=xyz)\n", featurestr);
|
||||
goto error;
|
||||
}
|
||||
featurestr = strtok(NULL, ",");
|
||||
}
|
||||
cpu_def->features |= plus_features;
|
||||
cpu_def->features &= ~minus_features;
|
||||
#ifdef DEBUG_FEATURES
|
||||
print_features(stderr, fprintf, cpu_def->features, NULL);
|
||||
#endif
|
||||
free(s);
|
||||
return 0;
|
||||
|
||||
error:
|
||||
free(s);
|
||||
return -1;
|
||||
}
|
||||
|
||||
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
|
||||
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx
|
||||
" FPU %08x MMU %08x NWINS %d ",
|
||||
sparc_defs[i].name,
|
||||
sparc_defs[i].iu_version,
|
||||
sparc_defs[i].fpu_version,
|
||||
sparc_defs[i].mmu_version,
|
||||
sparc_defs[i].nwindows);
|
||||
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES &
|
||||
~sparc_defs[i].features, "-");
|
||||
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES &
|
||||
sparc_defs[i].features, "+");
|
||||
(*cpu_fprintf)(f, "\n");
|
||||
}
|
||||
(*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
||||
print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
||||
(*cpu_fprintf)(f, "\n");
|
||||
(*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
||||
print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
||||
(*cpu_fprintf)(f, "\n");
|
||||
(*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
||||
"fpu_version mmu_version nwindows\n");
|
||||
}
|
||||
|
||||
static void cpu_print_cc(FILE *f, fprintf_function cpu_fprintf,
|
||||
uint32_t cc)
|
||||
{
|
||||
cpu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
|
||||
cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
|
||||
cc & PSR_CARRY ? 'C' : '-');
|
||||
}
|
||||
|
||||
#ifdef TARGET_SPARC64
|
||||
#define REGS_PER_LINE 4
|
||||
#else
|
||||
#define REGS_PER_LINE 8
|
||||
#endif
|
||||
|
||||
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
||||
int flags)
|
||||
{
|
||||
int i, x;
|
||||
|
||||
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
|
||||
env->npc);
|
||||
cpu_fprintf(f, "General Registers:\n");
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (i % REGS_PER_LINE == 0) {
|
||||
cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
|
||||
}
|
||||
cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
|
||||
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
||||
cpu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
cpu_fprintf(f, "\nCurrent Register Window:\n");
|
||||
for (x = 0; x < 3; x++) {
|
||||
for (i = 0; i < 8; i++) {
|
||||
if (i % REGS_PER_LINE == 0) {
|
||||
cpu_fprintf(f, "%%%c%d-%d: ",
|
||||
x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
|
||||
i, i + REGS_PER_LINE - 1);
|
||||
}
|
||||
cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
|
||||
if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
|
||||
cpu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
cpu_fprintf(f, "\nFloating Point Registers:\n");
|
||||
for (i = 0; i < TARGET_FPREGS; i++) {
|
||||
if ((i & 3) == 0) {
|
||||
cpu_fprintf(f, "%%f%02d:", i);
|
||||
}
|
||||
cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]);
|
||||
if ((i & 3) == 3) {
|
||||
cpu_fprintf(f, "\n");
|
||||
}
|
||||
}
|
||||
#ifdef TARGET_SPARC64
|
||||
cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
|
||||
(unsigned)cpu_get_ccr(env));
|
||||
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
|
||||
cpu_fprintf(f, " xcc: ");
|
||||
cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
|
||||
cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl,
|
||||
env->psrpil);
|
||||
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
|
||||
"cleanwin: %d cwp: %d\n",
|
||||
env->cansave, env->canrestore, env->otherwin, env->wstate,
|
||||
env->cleanwin, env->nwindows - 1 - env->cwp);
|
||||
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: "
|
||||
TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs);
|
||||
#else
|
||||
cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
|
||||
cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env));
|
||||
cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
|
||||
env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
|
||||
env->wim);
|
||||
cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
|
||||
env->fsr, env->y);
|
||||
#endif
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
125
target-sparc/int32_helper.c
Normal file
125
target-sparc/int32_helper.c
Normal file
@ -0,0 +1,125 @@
|
||||
/*
|
||||
* Sparc32 interrupt helpers
|
||||
*
|
||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
//#define DEBUG_PCALL
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
static const char * const excp_names[0x80] = {
|
||||
[TT_TFAULT] = "Instruction Access Fault",
|
||||
[TT_ILL_INSN] = "Illegal Instruction",
|
||||
[TT_PRIV_INSN] = "Privileged Instruction",
|
||||
[TT_NFPU_INSN] = "FPU Disabled",
|
||||
[TT_WIN_OVF] = "Window Overflow",
|
||||
[TT_WIN_UNF] = "Window Underflow",
|
||||
[TT_UNALIGNED] = "Unaligned Memory Access",
|
||||
[TT_FP_EXCP] = "FPU Exception",
|
||||
[TT_DFAULT] = "Data Access Fault",
|
||||
[TT_TOVF] = "Tag Overflow",
|
||||
[TT_EXTINT | 0x1] = "External Interrupt 1",
|
||||
[TT_EXTINT | 0x2] = "External Interrupt 2",
|
||||
[TT_EXTINT | 0x3] = "External Interrupt 3",
|
||||
[TT_EXTINT | 0x4] = "External Interrupt 4",
|
||||
[TT_EXTINT | 0x5] = "External Interrupt 5",
|
||||
[TT_EXTINT | 0x6] = "External Interrupt 6",
|
||||
[TT_EXTINT | 0x7] = "External Interrupt 7",
|
||||
[TT_EXTINT | 0x8] = "External Interrupt 8",
|
||||
[TT_EXTINT | 0x9] = "External Interrupt 9",
|
||||
[TT_EXTINT | 0xa] = "External Interrupt 10",
|
||||
[TT_EXTINT | 0xb] = "External Interrupt 11",
|
||||
[TT_EXTINT | 0xc] = "External Interrupt 12",
|
||||
[TT_EXTINT | 0xd] = "External Interrupt 13",
|
||||
[TT_EXTINT | 0xe] = "External Interrupt 14",
|
||||
[TT_EXTINT | 0xf] = "External Interrupt 15",
|
||||
[TT_TOVF] = "Tag Overflow",
|
||||
[TT_CODE_ACCESS] = "Instruction Access Error",
|
||||
[TT_DATA_ACCESS] = "Data Access Error",
|
||||
[TT_DIV_ZERO] = "Division By Zero",
|
||||
[TT_NCP_INSN] = "Coprocessor Disabled",
|
||||
};
|
||||
#endif
|
||||
|
||||
void do_interrupt(CPUState *env)
|
||||
{
|
||||
int cwp, intno = env->exception_index;
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
||||
static int count;
|
||||
const char *name;
|
||||
|
||||
if (intno < 0 || intno >= 0x100) {
|
||||
name = "Unknown";
|
||||
} else if (intno >= 0x80) {
|
||||
name = "Trap Instruction";
|
||||
} else {
|
||||
name = excp_names[intno];
|
||||
if (!name) {
|
||||
name = "Unknown";
|
||||
}
|
||||
}
|
||||
|
||||
qemu_log("%6d: %s (v=%02x) pc=%08x npc=%08x SP=%08x\n",
|
||||
count, name, intno,
|
||||
env->pc,
|
||||
env->npc, env->regwptr[6]);
|
||||
log_cpu_state(env, 0);
|
||||
#if 0
|
||||
{
|
||||
int i;
|
||||
uint8_t *ptr;
|
||||
|
||||
qemu_log(" code=");
|
||||
ptr = (uint8_t *)env->pc;
|
||||
for (i = 0; i < 16; i++) {
|
||||
qemu_log(" %02x", ldub(ptr + i));
|
||||
}
|
||||
qemu_log("\n");
|
||||
}
|
||||
#endif
|
||||
count++;
|
||||
}
|
||||
#endif
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
if (env->psret == 0) {
|
||||
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
|
||||
env->exception_index);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
env->psret = 0;
|
||||
cwp = cpu_cwp_dec(env, env->cwp - 1);
|
||||
cpu_set_cwp(env, cwp);
|
||||
env->regwptr[9] = env->pc;
|
||||
env->regwptr[10] = env->npc;
|
||||
env->psrps = env->psrs;
|
||||
env->psrs = 1;
|
||||
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
||||
env->pc = env->tbr;
|
||||
env->npc = env->pc + 4;
|
||||
env->exception_index = -1;
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* IRQ acknowledgment */
|
||||
if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
|
||||
env->qemu_irq_ack(env->irq_manager, intno);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
159
target-sparc/int64_helper.c
Normal file
159
target-sparc/int64_helper.c
Normal file
@ -0,0 +1,159 @@
|
||||
/*
|
||||
* Sparc64 interrupt helpers
|
||||
*
|
||||
* Copyright (c) 2003-2005 Fabrice Bellard
|
||||
*
|
||||
* This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU Lesser General Public
|
||||
* License as published by the Free Software Foundation; either
|
||||
* version 2 of the License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "cpu.h"
|
||||
|
||||
//#define DEBUG_PCALL
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
static const char * const excp_names[0x80] = {
|
||||
[TT_TFAULT] = "Instruction Access Fault",
|
||||
[TT_TMISS] = "Instruction Access MMU Miss",
|
||||
[TT_CODE_ACCESS] = "Instruction Access Error",
|
||||
[TT_ILL_INSN] = "Illegal Instruction",
|
||||
[TT_PRIV_INSN] = "Privileged Instruction",
|
||||
[TT_NFPU_INSN] = "FPU Disabled",
|
||||
[TT_FP_EXCP] = "FPU Exception",
|
||||
[TT_TOVF] = "Tag Overflow",
|
||||
[TT_CLRWIN] = "Clean Windows",
|
||||
[TT_DIV_ZERO] = "Division By Zero",
|
||||
[TT_DFAULT] = "Data Access Fault",
|
||||
[TT_DMISS] = "Data Access MMU Miss",
|
||||
[TT_DATA_ACCESS] = "Data Access Error",
|
||||
[TT_DPROT] = "Data Protection Error",
|
||||
[TT_UNALIGNED] = "Unaligned Memory Access",
|
||||
[TT_PRIV_ACT] = "Privileged Action",
|
||||
[TT_EXTINT | 0x1] = "External Interrupt 1",
|
||||
[TT_EXTINT | 0x2] = "External Interrupt 2",
|
||||
[TT_EXTINT | 0x3] = "External Interrupt 3",
|
||||
[TT_EXTINT | 0x4] = "External Interrupt 4",
|
||||
[TT_EXTINT | 0x5] = "External Interrupt 5",
|
||||
[TT_EXTINT | 0x6] = "External Interrupt 6",
|
||||
[TT_EXTINT | 0x7] = "External Interrupt 7",
|
||||
[TT_EXTINT | 0x8] = "External Interrupt 8",
|
||||
[TT_EXTINT | 0x9] = "External Interrupt 9",
|
||||
[TT_EXTINT | 0xa] = "External Interrupt 10",
|
||||
[TT_EXTINT | 0xb] = "External Interrupt 11",
|
||||
[TT_EXTINT | 0xc] = "External Interrupt 12",
|
||||
[TT_EXTINT | 0xd] = "External Interrupt 13",
|
||||
[TT_EXTINT | 0xe] = "External Interrupt 14",
|
||||
[TT_EXTINT | 0xf] = "External Interrupt 15",
|
||||
};
|
||||
#endif
|
||||
|
||||
void do_interrupt(CPUState *env)
|
||||
{
|
||||
int intno = env->exception_index;
|
||||
trap_state *tsptr;
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
||||
static int count;
|
||||
const char *name;
|
||||
|
||||
if (intno < 0 || intno >= 0x180) {
|
||||
name = "Unknown";
|
||||
} else if (intno >= 0x100) {
|
||||
name = "Trap Instruction";
|
||||
} else if (intno >= 0xc0) {
|
||||
name = "Window Fill";
|
||||
} else if (intno >= 0x80) {
|
||||
name = "Window Spill";
|
||||
} else {
|
||||
name = excp_names[intno];
|
||||
if (!name) {
|
||||
name = "Unknown";
|
||||
}
|
||||
}
|
||||
|
||||
qemu_log("%6d: %s (v=%04x) pc=%016" PRIx64 " npc=%016" PRIx64
|
||||
" SP=%016" PRIx64 "\n",
|
||||
count, name, intno,
|
||||
env->pc,
|
||||
env->npc, env->regwptr[6]);
|
||||
log_cpu_state(env, 0);
|
||||
#if 0
|
||||
{
|
||||
int i;
|
||||
uint8_t *ptr;
|
||||
|
||||
qemu_log(" code=");
|
||||
ptr = (uint8_t *)env->pc;
|
||||
for (i = 0; i < 16; i++) {
|
||||
qemu_log(" %02x", ldub(ptr + i));
|
||||
}
|
||||
qemu_log("\n");
|
||||
}
|
||||
#endif
|
||||
count++;
|
||||
}
|
||||
#endif
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
if (env->tl >= env->maxtl) {
|
||||
cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
|
||||
" Error state", env->exception_index, env->tl, env->maxtl);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
if (env->tl < env->maxtl - 1) {
|
||||
env->tl++;
|
||||
} else {
|
||||
env->pstate |= PS_RED;
|
||||
if (env->tl < env->maxtl) {
|
||||
env->tl++;
|
||||
}
|
||||
}
|
||||
tsptr = cpu_tsptr(env);
|
||||
|
||||
tsptr->tstate = (cpu_get_ccr(env) << 32) |
|
||||
((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
|
||||
cpu_get_cwp64(env);
|
||||
tsptr->tpc = env->pc;
|
||||
tsptr->tnpc = env->npc;
|
||||
tsptr->tt = intno;
|
||||
|
||||
switch (intno) {
|
||||
case TT_IVEC:
|
||||
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
|
||||
break;
|
||||
case TT_TFAULT:
|
||||
case TT_DFAULT:
|
||||
case TT_TMISS ... TT_TMISS + 3:
|
||||
case TT_DMISS ... TT_DMISS + 3:
|
||||
case TT_DPROT ... TT_DPROT + 3:
|
||||
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
|
||||
break;
|
||||
default:
|
||||
cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
|
||||
break;
|
||||
}
|
||||
|
||||
if (intno == TT_CLRWIN) {
|
||||
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
|
||||
} else if ((intno & 0x1c0) == TT_SPILL) {
|
||||
cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
|
||||
} else if ((intno & 0x1c0) == TT_FILL) {
|
||||
cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
|
||||
}
|
||||
env->tbr &= ~0x7fffULL;
|
||||
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
|
||||
env->pc = env->tbr;
|
||||
env->npc = env->pc + 4;
|
||||
env->exception_index = -1;
|
||||
}
|
||||
@ -13,7 +13,6 @@
|
||||
//#define DEBUG_UNALIGNED
|
||||
//#define DEBUG_UNASSIGNED
|
||||
//#define DEBUG_ASI
|
||||
//#define DEBUG_PCALL
|
||||
//#define DEBUG_PSTATE
|
||||
//#define DEBUG_CACHE_CONTROL
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user