ab3b491f21
Move CPU init to cpu_init.c and interrupt handling to int32_helper.c for Sparc32 and int64_helper.c for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
869 lines
27 KiB
C
869 lines
27 KiB
C
/*
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* sparc helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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//#define DEBUG_MMU
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_MMU(fmt, ...) do {} while (0)
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#endif
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/* Sparc MMU emulation */
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#if defined(CONFIG_USER_ONLY)
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int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
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int mmu_idx)
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{
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if (rw & 2)
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env1->exception_index = TT_TFAULT;
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else
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env1->exception_index = TT_DFAULT;
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return 1;
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}
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#else
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#ifndef TARGET_SPARC64
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/*
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* Sparc V8 Reference MMU (SRMMU)
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*/
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static const int access_table[8][8] = {
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{ 0, 0, 0, 0, 8, 0, 12, 12 },
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{ 0, 0, 0, 0, 8, 0, 0, 0 },
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{ 8, 8, 0, 0, 0, 8, 12, 12 },
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{ 8, 8, 0, 0, 0, 8, 0, 0 },
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{ 8, 0, 8, 0, 8, 8, 12, 12 },
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{ 8, 0, 8, 0, 8, 0, 8, 0 },
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{ 8, 8, 8, 0, 8, 8, 12, 12 },
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{ 8, 8, 8, 0, 8, 8, 8, 0 }
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};
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static const int perm_table[2][8] = {
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{
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PAGE_READ,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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PAGE_EXEC,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC
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},
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{
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PAGE_READ,
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PAGE_READ | PAGE_WRITE,
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PAGE_READ | PAGE_EXEC,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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PAGE_EXEC,
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PAGE_READ,
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0,
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0,
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}
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};
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static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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int *prot, int *access_index,
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target_ulong address, int rw, int mmu_idx,
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target_ulong *page_size)
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{
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int access_perms = 0;
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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int error_code = 0, is_dirty, is_user;
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unsigned long page_offset;
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is_user = mmu_idx == MMU_USER_IDX;
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
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*page_size = TARGET_PAGE_SIZE;
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// Boot mode: instruction fetches are taken from PROM
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if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC;
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return 0;
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}
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*physical = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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*physical = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1 << 2;
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case 2: /* L0 PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 4 << 2;
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case 1: /* L0 PDE */
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (1 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (1 << 8) | (4 << 2);
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case 1: /* L1 PDE */
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (2 << 8) | (1 << 2);
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case 3: /* Reserved */
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return (2 << 8) | (4 << 2);
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case 1: /* L2 PDE */
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return (3 << 8) | (1 << 2);
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return (3 << 8) | (4 << 2);
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case 2: /* L3 PTE */
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page_offset = (address & TARGET_PAGE_MASK) &
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(TARGET_PAGE_SIZE - 1);
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}
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*page_size = TARGET_PAGE_SIZE;
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break;
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case 2: /* L2 PTE */
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page_offset = address & 0x3ffff;
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*page_size = 0x40000;
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}
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break;
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case 2: /* L1 PTE */
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page_offset = address & 0xffffff;
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*page_size = 0x1000000;
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}
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}
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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error_code = access_table[*access_index][access_perms];
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
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return error_code;
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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pde |= PG_MODIFIED_MASK;
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stl_phys_notdirty(pde_ptr, pde);
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}
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/* the page can be put in the TLB */
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*prot = perm_table[is_user][access_perms];
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if (!(pde & PG_MODIFIED_MASK)) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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*prot &= ~PAGE_WRITE;
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}
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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}
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx)
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{
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target_phys_addr_t paddr;
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target_ulong vaddr;
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target_ulong page_size;
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int error_code = 0, prot, access_index;
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error_code = get_physical_address(env, &paddr, &prot, &access_index,
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address, rw, mmu_idx, &page_size);
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if (error_code == 0) {
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vaddr = address & TARGET_PAGE_MASK;
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paddr &= TARGET_PAGE_MASK;
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#ifdef DEBUG_MMU
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printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
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TARGET_FMT_lx "\n", address, paddr, vaddr);
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#endif
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
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return 0;
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}
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if (env->mmuregs[3]) /* Fault status register */
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */
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env->mmuregs[3] |= (access_index << 5) | error_code | 2;
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env->mmuregs[4] = address; /* Fault address register */
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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} else {
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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}
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target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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{
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target_phys_addr_t pde_ptr;
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uint32_t pde;
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/* Context base + context number */
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pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) +
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(env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 2: /* PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 0;
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case 1: /* L1 PDE */
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if (mmulev == 3)
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return pde;
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L1 PTE */
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return pde;
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case 1: /* L2 PDE */
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if (mmulev == 2)
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return pde;
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 3: /* Reserved */
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return 0;
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case 2: /* L2 PTE */
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return pde;
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case 1: /* L3 PDE */
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if (mmulev == 1)
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return pde;
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return 0;
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case 2: /* L3 PTE */
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return pde;
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}
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}
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}
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}
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return 0;
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}
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void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
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{
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target_ulong va, va1, va2;
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unsigned int n, m, o;
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target_phys_addr_t pde_ptr, pa;
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uint32_t pde;
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
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pde = ldl_phys(pde_ptr);
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(*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
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(target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]);
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for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
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pde = mmu_probe(env, va, 2);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va);
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(*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
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" PDE: " TARGET_FMT_lx "\n", va, pa, pde);
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for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
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pde = mmu_probe(env, va1, 1);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va1);
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(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
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TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
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va1, pa, pde);
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for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
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pde = mmu_probe(env, va2, 0);
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if (pde) {
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pa = cpu_get_phys_page_debug(env, va2);
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(*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
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TARGET_FMT_plx " PTE: "
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TARGET_FMT_lx "\n",
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va2, pa, pde);
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}
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}
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}
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}
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}
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}
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}
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/* Gdb expects all registers windows to be flushed in ram. This function handles
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* reads (and only reads) in stack frames as if windows were flushed. We assume
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* that the sparc ABI is followed.
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*/
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int target_memory_rw_debug(CPUState *env, target_ulong addr,
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uint8_t *buf, int len, int is_write)
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{
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int i;
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int len1;
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int cwp = env->cwp;
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if (!is_write) {
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for (i = 0; i < env->nwindows; i++) {
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int off;
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target_ulong fp = env->regbase[cwp * 16 + 22];
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/* Assume fp == 0 means end of frame. */
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if (fp == 0) {
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break;
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}
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cwp = cpu_cwp_inc(env, cwp + 1);
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/* Invalid window ? */
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if (env->wim & (1 << cwp)) {
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break;
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}
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/* According to the ABI, the stack is growing downward. */
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if (addr + len < fp) {
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break;
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}
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/* Not in this frame. */
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if (addr > fp + 64) {
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continue;
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}
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/* Handle access before this window. */
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if (addr < fp) {
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len1 = fp - addr;
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if (cpu_memory_rw_debug(env, addr, buf, len1, is_write) != 0) {
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return -1;
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}
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addr += len1;
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len -= len1;
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buf += len1;
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}
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/* Access byte per byte to registers. Not very efficient but speed
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* is not critical.
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*/
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off = addr - fp;
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len1 = 64 - off;
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if (len1 > len) {
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len1 = len;
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}
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for (; len1; len1--) {
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int reg = cwp * 16 + 8 + (off >> 2);
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union {
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uint32_t v;
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uint8_t c[4];
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} u;
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u.v = cpu_to_be32(env->regbase[reg]);
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*buf++ = u.c[off & 3];
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addr++;
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len--;
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off++;
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}
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if (len == 0) {
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return 0;
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}
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}
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}
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return cpu_memory_rw_debug(env, addr, buf, len, is_write);
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}
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#else /* !TARGET_SPARC64 */
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// 41 bit physical address space
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static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
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{
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return x & 0x1ffffffffffULL;
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}
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/*
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* UltraSparc IIi I/DMMUs
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*/
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// Returns true if TTE tag is valid and matches virtual address value in context
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// requires virtual address mask value calculated from TTE entry size
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static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
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uint64_t address, uint64_t context,
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target_phys_addr_t *physical)
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{
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uint64_t mask;
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switch (TTE_PGSIZE(tlb->tte)) {
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default:
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case 0x0: // 8k
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mask = 0xffffffffffffe000ULL;
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break;
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case 0x1: // 64k
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mask = 0xffffffffffff0000ULL;
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break;
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case 0x2: // 512k
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mask = 0xfffffffffff80000ULL;
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break;
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case 0x3: // 4M
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mask = 0xffffffffffc00000ULL;
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break;
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}
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// valid, context match, virtual address match?
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if (TTE_IS_VALID(tlb->tte) &&
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(TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
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&& compare_masked(address, tlb->tag, mask))
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{
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// decode physical address
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*physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
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return 1;
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}
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return 0;
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}
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static int get_physical_address_data(CPUState *env,
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target_phys_addr_t *physical, int *prot,
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target_ulong address, int rw, int mmu_idx)
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{
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unsigned int i;
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uint64_t context;
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uint64_t sfsr = 0;
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int is_user = (mmu_idx == MMU_USER_IDX ||
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mmu_idx == MMU_USER_SECONDARY_IDX);
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
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*physical = ultrasparc_truncate_physical(address);
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*prot = PAGE_READ | PAGE_WRITE;
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return 0;
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}
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switch(mmu_idx) {
|
|
case MMU_USER_IDX:
|
|
case MMU_KERNEL_IDX:
|
|
context = env->dmmu.mmu_primary_context & 0x1fff;
|
|
sfsr |= SFSR_CT_PRIMARY;
|
|
break;
|
|
case MMU_USER_SECONDARY_IDX:
|
|
case MMU_KERNEL_SECONDARY_IDX:
|
|
context = env->dmmu.mmu_secondary_context & 0x1fff;
|
|
sfsr |= SFSR_CT_SECONDARY;
|
|
break;
|
|
case MMU_NUCLEUS_IDX:
|
|
sfsr |= SFSR_CT_NUCLEUS;
|
|
/* FALLTHRU */
|
|
default:
|
|
context = 0;
|
|
break;
|
|
}
|
|
|
|
if (rw == 1) {
|
|
sfsr |= SFSR_WRITE_BIT;
|
|
} else if (rw == 4) {
|
|
sfsr |= SFSR_NF_BIT;
|
|
}
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
// ctx match, vaddr match, valid?
|
|
if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
|
|
int do_fault = 0;
|
|
|
|
// access ok?
|
|
/* multiple bits in SFSR.FT may be set on TT_DFAULT */
|
|
if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
|
|
do_fault = 1;
|
|
sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
|
|
|
|
DPRINTF_MMU("DFAULT at %" PRIx64 " context %" PRIx64
|
|
" mmu_idx=%d tl=%d\n",
|
|
address, context, mmu_idx, env->tl);
|
|
}
|
|
if (rw == 4) {
|
|
if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
|
|
do_fault = 1;
|
|
sfsr |= SFSR_FT_NF_E_BIT;
|
|
}
|
|
} else {
|
|
if (TTE_IS_NFO(env->dtlb[i].tte)) {
|
|
do_fault = 1;
|
|
sfsr |= SFSR_FT_NFO_BIT;
|
|
}
|
|
}
|
|
|
|
if (do_fault) {
|
|
/* faults above are reported with TT_DFAULT. */
|
|
env->exception_index = TT_DFAULT;
|
|
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
|
|
do_fault = 1;
|
|
env->exception_index = TT_DPROT;
|
|
|
|
DPRINTF_MMU("DPROT at %" PRIx64 " context %" PRIx64
|
|
" mmu_idx=%d tl=%d\n",
|
|
address, context, mmu_idx, env->tl);
|
|
}
|
|
|
|
if (!do_fault) {
|
|
*prot = PAGE_READ;
|
|
if (TTE_IS_W_OK(env->dtlb[i].tte)) {
|
|
*prot |= PAGE_WRITE;
|
|
}
|
|
|
|
TTE_SET_USED(env->dtlb[i].tte);
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
|
|
sfsr |= SFSR_OW_BIT; /* overflow (not read before
|
|
another fault) */
|
|
}
|
|
|
|
if (env->pstate & PS_PRIV) {
|
|
sfsr |= SFSR_PR_BIT;
|
|
}
|
|
|
|
/* FIXME: ASI field in SFSR must be set */
|
|
env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
|
|
|
|
env->dmmu.sfar = address; /* Fault address register */
|
|
|
|
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
|
|
|
return 1;
|
|
}
|
|
}
|
|
|
|
DPRINTF_MMU("DMISS at %" PRIx64 " context %" PRIx64 "\n",
|
|
address, context);
|
|
|
|
/*
|
|
* On MMU misses:
|
|
* - UltraSPARC IIi: SFSR and SFAR unmodified
|
|
* - JPS1: SFAR updated and some fields of SFSR updated
|
|
*/
|
|
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
|
|
env->exception_index = TT_DMISS;
|
|
return 1;
|
|
}
|
|
|
|
static int get_physical_address_code(CPUState *env,
|
|
target_phys_addr_t *physical, int *prot,
|
|
target_ulong address, int mmu_idx)
|
|
{
|
|
unsigned int i;
|
|
uint64_t context;
|
|
|
|
int is_user = (mmu_idx == MMU_USER_IDX ||
|
|
mmu_idx == MMU_USER_SECONDARY_IDX);
|
|
|
|
if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
|
|
/* IMMU disabled */
|
|
*physical = ultrasparc_truncate_physical(address);
|
|
*prot = PAGE_EXEC;
|
|
return 0;
|
|
}
|
|
|
|
if (env->tl == 0) {
|
|
/* PRIMARY context */
|
|
context = env->dmmu.mmu_primary_context & 0x1fff;
|
|
} else {
|
|
/* NUCLEUS context */
|
|
context = 0;
|
|
}
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
// ctx match, vaddr match, valid?
|
|
if (ultrasparc_tag_match(&env->itlb[i],
|
|
address, context, physical)) {
|
|
// access ok?
|
|
if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
|
|
/* Fault status register */
|
|
if (env->immu.sfsr & SFSR_VALID_BIT) {
|
|
env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
|
|
another fault) */
|
|
} else {
|
|
env->immu.sfsr = 0;
|
|
}
|
|
if (env->pstate & PS_PRIV) {
|
|
env->immu.sfsr |= SFSR_PR_BIT;
|
|
}
|
|
if (env->tl > 0) {
|
|
env->immu.sfsr |= SFSR_CT_NUCLEUS;
|
|
}
|
|
|
|
/* FIXME: ASI field in SFSR must be set */
|
|
env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
|
|
env->exception_index = TT_TFAULT;
|
|
|
|
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
|
|
|
DPRINTF_MMU("TFAULT at %" PRIx64 " context %" PRIx64 "\n",
|
|
address, context);
|
|
|
|
return 1;
|
|
}
|
|
*prot = PAGE_EXEC;
|
|
TTE_SET_USED(env->itlb[i].tte);
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
DPRINTF_MMU("TMISS at %" PRIx64 " context %" PRIx64 "\n",
|
|
address, context);
|
|
|
|
/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
|
|
env->immu.tag_access = (address & ~0x1fffULL) | context;
|
|
env->exception_index = TT_TMISS;
|
|
return 1;
|
|
}
|
|
|
|
static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
|
|
int *prot, int *access_index,
|
|
target_ulong address, int rw, int mmu_idx,
|
|
target_ulong *page_size)
|
|
{
|
|
/* ??? We treat everything as a small page, then explicitly flush
|
|
everything when an entry is evicted. */
|
|
*page_size = TARGET_PAGE_SIZE;
|
|
|
|
#if defined (DEBUG_MMU)
|
|
/* safety net to catch wrong softmmu index use from dynamic code */
|
|
if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
|
|
DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
|
|
" primary context=%" PRIx64
|
|
" secondary context=%" PRIx64
|
|
" address=%" PRIx64
|
|
"\n",
|
|
(rw == 2 ? "CODE" : "DATA"),
|
|
env->tl, mmu_idx,
|
|
env->dmmu.mmu_primary_context,
|
|
env->dmmu.mmu_secondary_context,
|
|
address);
|
|
}
|
|
#endif
|
|
|
|
if (rw == 2)
|
|
return get_physical_address_code(env, physical, prot, address,
|
|
mmu_idx);
|
|
else
|
|
return get_physical_address_data(env, physical, prot, address, rw,
|
|
mmu_idx);
|
|
}
|
|
|
|
/* Perform address translation */
|
|
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
|
|
int mmu_idx)
|
|
{
|
|
target_ulong virt_addr, vaddr;
|
|
target_phys_addr_t paddr;
|
|
target_ulong page_size;
|
|
int error_code = 0, prot, access_index;
|
|
|
|
error_code = get_physical_address(env, &paddr, &prot, &access_index,
|
|
address, rw, mmu_idx, &page_size);
|
|
if (error_code == 0) {
|
|
virt_addr = address & TARGET_PAGE_MASK;
|
|
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) &
|
|
(TARGET_PAGE_SIZE - 1));
|
|
|
|
DPRINTF_MMU("Translate at %" PRIx64 " -> %" PRIx64 ","
|
|
" vaddr %" PRIx64
|
|
" mmu_idx=%d"
|
|
" tl=%d"
|
|
" primary context=%" PRIx64
|
|
" secondary context=%" PRIx64
|
|
"\n",
|
|
address, paddr, vaddr, mmu_idx, env->tl,
|
|
env->dmmu.mmu_primary_context,
|
|
env->dmmu.mmu_secondary_context);
|
|
|
|
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
|
|
return 0;
|
|
}
|
|
// XXX
|
|
return 1;
|
|
}
|
|
|
|
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
|
|
{
|
|
unsigned int i;
|
|
const char *mask;
|
|
|
|
(*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
|
|
PRId64 "\n",
|
|
env->dmmu.mmu_primary_context,
|
|
env->dmmu.mmu_secondary_context);
|
|
if ((env->lsu & DMMU_E) == 0) {
|
|
(*cpu_fprintf)(f, "DMMU disabled\n");
|
|
} else {
|
|
(*cpu_fprintf)(f, "DMMU dump\n");
|
|
for (i = 0; i < 64; i++) {
|
|
switch (TTE_PGSIZE(env->dtlb[i].tte)) {
|
|
default:
|
|
case 0x0:
|
|
mask = " 8k";
|
|
break;
|
|
case 0x1:
|
|
mask = " 64k";
|
|
break;
|
|
case 0x2:
|
|
mask = "512k";
|
|
break;
|
|
case 0x3:
|
|
mask = " 4M";
|
|
break;
|
|
}
|
|
if (TTE_IS_VALID(env->dtlb[i].tte)) {
|
|
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
|
|
", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
|
|
i,
|
|
env->dtlb[i].tag & (uint64_t)~0x1fffULL,
|
|
TTE_PA(env->dtlb[i].tte),
|
|
mask,
|
|
TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
|
|
TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
|
|
TTE_IS_LOCKED(env->dtlb[i].tte) ?
|
|
"locked" : "unlocked",
|
|
env->dtlb[i].tag & (uint64_t)0x1fffULL,
|
|
TTE_IS_GLOBAL(env->dtlb[i].tte)?
|
|
"global" : "local");
|
|
}
|
|
}
|
|
}
|
|
if ((env->lsu & IMMU_E) == 0) {
|
|
(*cpu_fprintf)(f, "IMMU disabled\n");
|
|
} else {
|
|
(*cpu_fprintf)(f, "IMMU dump\n");
|
|
for (i = 0; i < 64; i++) {
|
|
switch (TTE_PGSIZE(env->itlb[i].tte)) {
|
|
default:
|
|
case 0x0:
|
|
mask = " 8k";
|
|
break;
|
|
case 0x1:
|
|
mask = " 64k";
|
|
break;
|
|
case 0x2:
|
|
mask = "512k";
|
|
break;
|
|
case 0x3:
|
|
mask = " 4M";
|
|
break;
|
|
}
|
|
if (TTE_IS_VALID(env->itlb[i].tte)) {
|
|
(*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
|
|
", %s, %s, %s, ctx %" PRId64 " %s\n",
|
|
i,
|
|
env->itlb[i].tag & (uint64_t)~0x1fffULL,
|
|
TTE_PA(env->itlb[i].tte),
|
|
mask,
|
|
TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
|
|
TTE_IS_LOCKED(env->itlb[i].tte) ?
|
|
"locked" : "unlocked",
|
|
env->itlb[i].tag & (uint64_t)0x1fffULL,
|
|
TTE_IS_GLOBAL(env->itlb[i].tte)?
|
|
"global" : "local");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif /* TARGET_SPARC64 */
|
|
|
|
static int cpu_sparc_get_phys_page(CPUState *env, target_phys_addr_t *phys,
|
|
target_ulong addr, int rw, int mmu_idx)
|
|
{
|
|
target_ulong page_size;
|
|
int prot, access_index;
|
|
|
|
return get_physical_address(env, phys, &prot, &access_index, addr, rw,
|
|
mmu_idx, &page_size);
|
|
}
|
|
|
|
#if defined(TARGET_SPARC64)
|
|
target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
|
|
int mmu_idx)
|
|
{
|
|
target_phys_addr_t phys_addr;
|
|
|
|
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
|
|
return -1;
|
|
}
|
|
return phys_addr;
|
|
}
|
|
#endif
|
|
|
|
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
|
|
{
|
|
target_phys_addr_t phys_addr;
|
|
int mmu_idx = cpu_mmu_index(env);
|
|
|
|
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
|
|
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
|
|
return -1;
|
|
}
|
|
}
|
|
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED) {
|
|
return -1;
|
|
}
|
|
return phys_addr;
|
|
}
|
|
#endif
|