cpu: Move reset logging to CPUState
x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
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@ -53,6 +53,7 @@ typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
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* @class_by_name: Callback to map -cpu command line model name to an
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* instantiatable CPU type.
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* @reset: Callback to reset the #CPUState to its initial state.
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* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
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* @do_interrupt: Callback for interrupt handling.
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* @do_unassigned_access: Callback for unassigned access handling.
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* @dump_state: Callback for dumping state.
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@ -72,6 +73,7 @@ typedef struct CPUClass {
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ObjectClass *(*class_by_name)(const char *cpu_model);
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void (*reset)(CPUState *cpu);
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int reset_dump_flags;
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void (*do_interrupt)(CPUState *cpu);
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CPUUnassignedAccess do_unassigned_access;
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void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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@ -22,6 +22,7 @@
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#include "qom/cpu.h"
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#include "sysemu/kvm.h"
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#include "qemu/notify.h"
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#include "qemu/log.h"
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#include "sysemu/sysemu.h"
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typedef struct CPUExistsArgs {
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@ -187,6 +188,13 @@ void cpu_reset(CPUState *cpu)
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static void cpu_common_reset(CPUState *cpu)
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{
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CPUClass *cc = CPU_GET_CLASS(cpu);
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index);
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log_cpu_state(cpu, cc->reset_dump_flags);
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}
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cpu->exit_request = 0;
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cpu->interrupt_request = 0;
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cpu->current_tb = NULL;
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@ -63,11 +63,6 @@ static void arm_cpu_reset(CPUState *s)
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ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
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CPUARMState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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acc->parent_reset(s);
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memset(env, 0, offsetof(CPUARMState, breakpoints));
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@ -34,11 +34,6 @@ static void cris_cpu_reset(CPUState *s)
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CPUCRISState *env = &cpu->env;
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uint32_t vr;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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ccc->parent_reset(s);
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vr = env->pregs[PR_VR];
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@ -2175,11 +2175,6 @@ static void x86_cpu_reset(CPUState *s)
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CPUX86State *env = &cpu->env;
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int i;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, CPU_DUMP_FPU | CPU_DUMP_CCOP);
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}
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xcc->parent_reset(s);
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@ -2523,6 +2518,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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xcc->parent_reset = cc->reset;
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cc->reset = x86_cpu_reset;
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cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
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cc->do_interrupt = x86_cpu_do_interrupt;
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cc->dump_state = x86_cpu_dump_state;
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@ -29,11 +29,6 @@ static void lm32_cpu_reset(CPUState *s)
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LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
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CPULM32State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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lcc->parent_reset(s);
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/* reset cpu state */
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@ -35,11 +35,6 @@ static void m68k_cpu_reset(CPUState *s)
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M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu);
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CPUM68KState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUM68KState, breakpoints));
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@ -33,11 +33,6 @@ static void mb_cpu_reset(CPUState *s)
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
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CPUMBState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMBState, breakpoints));
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@ -29,11 +29,6 @@ static void mips_cpu_reset(CPUState *s)
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MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
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CPUMIPSState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMIPSState, breakpoints));
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@ -28,11 +28,6 @@ static void moxie_cpu_reset(CPUState *s)
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MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu);
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CPUMoxieState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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mcc->parent_reset(s);
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memset(env, 0, offsetof(CPUMoxieState, breakpoints));
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@ -26,11 +26,6 @@ static void openrisc_cpu_reset(CPUState *s)
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OpenRISCCPU *cpu = OPENRISC_CPU(s);
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OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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occ->parent_reset(s);
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memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
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@ -8171,11 +8171,6 @@ static void ppc_cpu_reset(CPUState *s)
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CPUPPCState *env = &cpu->env;
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target_ulong msr;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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pcc->parent_reset(s);
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msr = (target_ulong)0;
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@ -65,11 +65,6 @@ static void s390_cpu_reset(CPUState *s)
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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s390_del_running_cpu(cpu);
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scc->parent_reset(s);
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@ -31,11 +31,6 @@ static void superh_cpu_reset(CPUState *s)
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SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
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CPUSH4State *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUSH4State, breakpoints));
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@ -30,11 +30,6 @@ static void sparc_cpu_reset(CPUState *s)
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
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CPUSPARCState *env = &cpu->env;
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if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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log_cpu_state(s, 0);
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}
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUSPARCState, breakpoints));
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