target/arm: Convert SUQADD and USQADD to gvec
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240528203044.612851-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
01d5665bc3
commit
8f6343ae18
@ -836,6 +836,22 @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_usqadd_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_usqadd_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_usqadd_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_usqadd_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_suqadd_b, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_suqadd_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_suqadd_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_suqadd_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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@ -188,3 +188,113 @@ void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op);
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}
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static void gen_suqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc,
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TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec max =
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tcg_constant_vec_matching(t, vece, (1ull << ((8 << vece) - 1)) - 1);
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TCGv_vec u = tcg_temp_new_vec_matching(t);
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/* Maximum value that can be added to @a without overflow. */
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tcg_gen_sub_vec(vece, u, max, a);
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/* Constrain addend so that the next addition never overflows. */
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tcg_gen_umin_vec(vece, u, u, b);
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tcg_gen_add_vec(vece, t, u, a);
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/* Compute QC by comparing the adjusted @b. */
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tcg_gen_xor_vec(vece, u, u, b);
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tcg_gen_or_vec(vece, qc, qc, u);
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}
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void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs,
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uint32_t rn_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_add_vec, INDEX_op_sub_vec, INDEX_op_umin_vec, 0
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};
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static const GVecGen4 ops[4] = {
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{ .fniv = gen_suqadd_vec,
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.fno = gen_helper_gvec_suqadd_b,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_8 },
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{ .fniv = gen_suqadd_vec,
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.fno = gen_helper_gvec_suqadd_h,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_16 },
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{ .fniv = gen_suqadd_vec,
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.fno = gen_helper_gvec_suqadd_s,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_32 },
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{ .fniv = gen_suqadd_vec,
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.fno = gen_helper_gvec_suqadd_d,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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static void gen_usqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec qc,
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TCGv_vec a, TCGv_vec b)
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{
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TCGv_vec u = tcg_temp_new_vec_matching(t);
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TCGv_vec z = tcg_constant_vec_matching(t, vece, 0);
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/* Compute unsigned saturation of add for +b and sub for -b. */
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tcg_gen_neg_vec(vece, t, b);
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tcg_gen_usadd_vec(vece, u, a, b);
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tcg_gen_ussub_vec(vece, t, a, t);
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/* Select the correct result depending on the sign of b. */
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tcg_gen_cmpsel_vec(TCG_COND_LT, vece, t, b, z, t, u);
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/* Compute QC by comparing against the non-saturated result. */
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tcg_gen_add_vec(vece, u, a, b);
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tcg_gen_xor_vec(vece, u, u, t);
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tcg_gen_or_vec(vece, qc, qc, u);
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}
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void gen_gvec_usqadd_qc(unsigned vece, uint32_t rd_ofs,
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uint32_t rn_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz)
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{
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static const TCGOpcode vecop_list[] = {
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INDEX_op_neg_vec, INDEX_op_add_vec,
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INDEX_op_usadd_vec, INDEX_op_ussub_vec,
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INDEX_op_cmpsel_vec, 0
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};
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static const GVecGen4 ops[4] = {
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{ .fniv = gen_usqadd_vec,
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.fno = gen_helper_gvec_usqadd_b,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_8 },
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{ .fniv = gen_usqadd_vec,
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.fno = gen_helper_gvec_usqadd_h,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_16 },
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{ .fniv = gen_usqadd_vec,
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.fno = gen_helper_gvec_usqadd_s,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_32 },
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{ .fniv = gen_usqadd_vec,
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.fno = gen_helper_gvec_usqadd_d,
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.opt_opc = vecop_list,
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.write_aofs = true,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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@ -9983,83 +9983,68 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
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/* Remaining saturating accumulating ops */
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static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
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bool is_q, int size, int rn, int rd)
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bool is_q, unsigned size, int rn, int rd)
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{
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bool is_double = (size == 3);
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if (!is_scalar) {
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gen_gvec_fn3(s, is_q, rd, rd, rn,
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is_u ? gen_gvec_usqadd_qc : gen_gvec_suqadd_qc, size);
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return;
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}
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if (is_double) {
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if (size == 3) {
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TCGv_i64 tcg_rn = tcg_temp_new_i64();
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TCGv_i64 tcg_rd = tcg_temp_new_i64();
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int pass;
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for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
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read_vec_element(s, tcg_rn, rn, pass, MO_64);
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read_vec_element(s, tcg_rd, rd, pass, MO_64);
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read_vec_element(s, tcg_rn, rn, 0, MO_64);
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read_vec_element(s, tcg_rd, rd, 0, MO_64);
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if (is_u) { /* USQADD */
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gen_helper_neon_uqadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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} else { /* SUQADD */
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gen_helper_neon_sqadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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}
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write_vec_element(s, tcg_rd, rd, pass, MO_64);
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if (is_u) { /* USQADD */
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gen_helper_neon_uqadd_s64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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} else { /* SUQADD */
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gen_helper_neon_sqadd_u64(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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}
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clear_vec_high(s, !is_scalar, rd);
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write_vec_element(s, tcg_rd, rd, 0, MO_64);
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clear_vec_high(s, false, rd);
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} else {
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TCGv_i32 tcg_rn = tcg_temp_new_i32();
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TCGv_i32 tcg_rd = tcg_temp_new_i32();
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int pass, maxpasses;
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if (is_scalar) {
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maxpasses = 1;
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} else {
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maxpasses = is_q ? 4 : 2;
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read_vec_element_i32(s, tcg_rn, rn, 0, size);
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read_vec_element_i32(s, tcg_rd, rd, 0, size);
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if (is_u) { /* USQADD */
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switch (size) {
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case 0:
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gen_helper_neon_uqadd_s8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_uqadd_s16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_uqadd_s32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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} else { /* SUQADD */
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switch (size) {
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case 0:
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gen_helper_neon_sqadd_u8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_sqadd_u16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_sqadd_u32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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}
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for (pass = 0; pass < maxpasses; pass++) {
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if (is_scalar) {
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read_vec_element_i32(s, tcg_rn, rn, pass, size);
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read_vec_element_i32(s, tcg_rd, rd, pass, size);
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} else {
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read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
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read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
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}
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if (is_u) { /* USQADD */
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switch (size) {
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case 0:
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gen_helper_neon_uqadd_s8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_uqadd_s16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_uqadd_s32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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} else { /* SUQADD */
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switch (size) {
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case 0:
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gen_helper_neon_sqadd_u8(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 1:
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gen_helper_neon_sqadd_u16(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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case 2:
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gen_helper_neon_sqadd_u32(tcg_rd, tcg_env, tcg_rn, tcg_rd);
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (is_scalar) {
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write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
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}
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write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
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}
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clear_vec_high(s, is_q, rd);
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write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64);
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write_vec_element_i32(s, tcg_rd, rd, 0, MO_32);
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clear_vec_high(s, false, rd);
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}
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}
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@ -197,6 +197,12 @@ void gen_gvec_eor3(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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uint32_t a, uint32_t oprsz, uint32_t maxsz);
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void gen_gvec_bcax(unsigned vece, uint32_t d, uint32_t n, uint32_t m,
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uint32_t a, uint32_t oprsz, uint32_t maxsz);
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void gen_gvec_suqadd_qc(unsigned vece, uint32_t rd_ofs,
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uint32_t rn_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_gvec_usqadd_qc(unsigned vece, uint32_t rd_ofs,
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uint32_t rn_ofs, uint32_t rm_ofs,
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uint32_t opr_sz, uint32_t max_sz);
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void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
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void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int imm);
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@ -1555,6 +1555,14 @@ DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX)
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DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX)
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DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX)
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DO_SAT(gvec_usqadd_b, int, uint8_t, int8_t, +, 0, UINT8_MAX)
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DO_SAT(gvec_usqadd_h, int, uint16_t, int16_t, +, 0, UINT16_MAX)
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DO_SAT(gvec_usqadd_s, int64_t, uint32_t, int32_t, +, 0, UINT32_MAX)
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DO_SAT(gvec_suqadd_b, int, int8_t, uint8_t, +, INT8_MIN, INT8_MAX)
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DO_SAT(gvec_suqadd_h, int, int16_t, uint16_t, +, INT16_MIN, INT16_MAX)
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DO_SAT(gvec_suqadd_s, int64_t, int32_t, uint32_t, +, INT32_MIN, INT32_MAX)
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#undef DO_SAT
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void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn,
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@ -1645,6 +1653,62 @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
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clear_tail(d, oprsz, simd_maxsz(desc));
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}
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void HELPER(gvec_usqadd_d)(void *vd, void *vq, void *vn,
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void *vm, uint32_t desc)
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{
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intptr_t i, oprsz = simd_oprsz(desc);
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uint64_t *d = vd, *n = vn, *m = vm;
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bool q = false;
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for (i = 0; i < oprsz / 8; i++) {
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uint64_t nn = n[i];
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int64_t mm = m[i];
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uint64_t dd = nn + mm;
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if (mm < 0) {
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if (nn < (uint64_t)-mm) {
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dd = 0;
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q = true;
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}
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} else {
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if (dd < nn) {
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dd = UINT64_MAX;
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q = true;
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}
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}
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d[i] = dd;
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}
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if (q) {
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uint32_t *qc = vq;
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qc[0] = 1;
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}
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clear_tail(d, oprsz, simd_maxsz(desc));
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}
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void HELPER(gvec_suqadd_d)(void *vd, void *vq, void *vn,
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void *vm, uint32_t desc)
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{
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intptr_t i, oprsz = simd_oprsz(desc);
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uint64_t *d = vd, *n = vn, *m = vm;
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bool q = false;
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for (i = 0; i < oprsz / 8; i++) {
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int64_t nn = n[i];
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uint64_t mm = m[i];
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int64_t dd = nn + mm;
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if (mm > (uint64_t)(INT64_MAX - nn)) {
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dd = INT64_MAX;
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q = true;
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}
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d[i] = dd;
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}
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if (q) {
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uint32_t *qc = vq;
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qc[0] = 1;
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}
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clear_tail(d, oprsz, simd_maxsz(desc));
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}
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#define DO_SRA(NAME, TYPE) \
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void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
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