target/arm: Assert oprsz in range when using vfp.qc
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240528203044.612851-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -29,6 +29,7 @@ static void gen_gvec_fn3_qc(uint32_t rd_ofs, uint32_t rn_ofs, uint32_t rm_ofs,
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{
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TCGv_ptr qc_ptr = tcg_temp_new_ptr();
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_addi_ptr(qc_ptr, tcg_env, offsetof(CPUARMState, vfp.qc));
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tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, qc_ptr,
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opr_sz, max_sz, 0, fn);
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@ -1255,6 +1256,8 @@ void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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.opt_opc = vecop_list,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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@ -1297,6 +1300,8 @@ void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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.write_aofs = true,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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@ -1339,6 +1344,8 @@ void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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.write_aofs = true,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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@ -1381,6 +1388,8 @@ void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
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.write_aofs = true,
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.vece = MO_64 },
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};
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tcg_debug_assert(opr_sz <= sizeof_field(CPUARMState, vfp.qc));
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tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
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rn_ofs, rm_ofs, opr_sz, max_sz, &ops[vece]);
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}
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