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char: cadence_uart: Split state struct and type into header

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Create a new header for Cadence UART to allow using the device with
modern SoC programming conventions. The state struct needs to be
visible to embed the device in SoC containers.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 46a0fbd45b6b205f54c4a8c778deb75c77f8abdf.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Crosthwaite 2015-05-14 19:23:18 -07:00 committed by Peter Maydell
parent e86da3cb40
commit 8ae57b2fa3
2 changed files with 54 additions and 28 deletions
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29
hw/char/cadence_uart.c
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@ -16,9 +16,7 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "hw/sysbus.h"
#include "sysemu/char.h"
#include "qemu/timer.h"
#include "hw/char/cadence_uart.h"
#ifdef CADENCE_UART_ERR_DEBUG
#define DB_PRINT(...) do { \
@ -85,8 +83,6 @@
#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
#define CADENCE_UART_RX_FIFO_SIZE 16
#define CADENCE_UART_TX_FIFO_SIZE 16
#define UART_INPUT_CLK 50000000
#define R_CR (0x00/4)
@ -108,29 +104,6 @@
#define R_PWID (0x40/4)
#define R_TTRIG (0x44/4)
#define CADENCE_UART_R_MAX (0x48/4)
#define TYPE_CADENCE_UART "cadence_uart"
#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
TYPE_CADENCE_UART)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t r[CADENCE_UART_R_MAX];
uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
uint32_t rx_wpos;
uint32_t rx_count;
uint32_t tx_count;
uint64_t char_tx_time;
CharDriverState *chr;
qemu_irq irq;
QEMUTimer *fifo_trigger_handle;
} CadenceUARTState;
static void uart_update_status(CadenceUARTState *s)
{

53
include/hw/char/cadence_uart.h Normal file
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@ -0,0 +1,53 @@
/*
* Device model for Cadence UART
*
* Copyright (c) 2010 Xilinx Inc.
* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
* Copyright (c) 2012 PetaLogix Pty Ltd.
* Written by Haibing Ma
* M.Habib
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CADENCE_UART_H
#include "hw/sysbus.h"
#include "sysemu/char.h"
#include "qemu/timer.h"
#define CADENCE_UART_RX_FIFO_SIZE 16
#define CADENCE_UART_TX_FIFO_SIZE 16
#define CADENCE_UART_R_MAX (0x48/4)
#define TYPE_CADENCE_UART "cadence_uart"
#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
TYPE_CADENCE_UART)
typedef struct {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
MemoryRegion iomem;
uint32_t r[CADENCE_UART_R_MAX];
uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
uint32_t rx_wpos;
uint32_t rx_count;
uint32_t tx_count;
uint64_t char_tx_time;
CharDriverState *chr;
qemu_irq irq;
QEMUTimer *fifo_trigger_handle;
} CadenceUARTState;
#define CADENCE_UART_H
#endif