char: cadence_uart: Clean up variable names
Clean up some variable names in preparation for migrating the state struct and type cast macro to a public header. The acronym "UART" on it's own is not specific enough to be used in a more global namespace so preface with "cadence". Fix the capitalisation of "uart" in the state type while touching the typename. Preface macros used by the state struct itself with CADENCE_UART so they don't conflict in namespace either. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3812b7426c338beae9e082557f3524a99310ddc6.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -85,8 +85,8 @@
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#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
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#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
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#define RX_FIFO_SIZE 16
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#define TX_FIFO_SIZE 16
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#define CADENCE_UART_RX_FIFO_SIZE 16
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#define CADENCE_UART_TX_FIFO_SIZE 16
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#define UART_INPUT_CLK 50000000
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#define R_CR (0x00/4)
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@ -108,10 +108,11 @@
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#define R_PWID (0x40/4)
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#define R_TTRIG (0x44/4)
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#define R_MAX (R_TTRIG + 1)
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#define CADENCE_UART_R_MAX (0x48/4)
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#define TYPE_CADENCE_UART "cadence_uart"
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#define CADENCE_UART(obj) OBJECT_CHECK(UartState, (obj), TYPE_CADENCE_UART)
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#define CADENCE_UART(obj) OBJECT_CHECK(CadenceUARTState, (obj), \
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TYPE_CADENCE_UART)
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typedef struct {
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/*< private >*/
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@ -119,9 +120,9 @@ typedef struct {
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/*< public >*/
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MemoryRegion iomem;
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uint32_t r[R_MAX];
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uint8_t rx_fifo[RX_FIFO_SIZE];
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uint8_t tx_fifo[TX_FIFO_SIZE];
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uint32_t r[CADENCE_UART_R_MAX];
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uint8_t rx_fifo[CADENCE_UART_RX_FIFO_SIZE];
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uint8_t tx_fifo[CADENCE_UART_TX_FIFO_SIZE];
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uint32_t rx_wpos;
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uint32_t rx_count;
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uint32_t tx_count;
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@ -129,17 +130,19 @@ typedef struct {
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CharDriverState *chr;
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qemu_irq irq;
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QEMUTimer *fifo_trigger_handle;
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} UartState;
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} CadenceUARTState;
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static void uart_update_status(UartState *s)
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static void uart_update_status(CadenceUARTState *s)
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{
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s->r[R_SR] = 0;
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s->r[R_SR] |= s->rx_count == RX_FIFO_SIZE ? UART_SR_INTR_RFUL : 0;
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s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
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: 0;
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s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
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s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
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s->r[R_SR] |= s->tx_count == TX_FIFO_SIZE ? UART_SR_INTR_TFUL : 0;
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s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
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: 0;
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s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
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s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
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@ -150,14 +153,14 @@ static void uart_update_status(UartState *s)
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static void fifo_trigger_update(void *opaque)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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s->r[R_CISR] |= UART_INTR_TIMEOUT;
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uart_update_status(s);
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}
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static void uart_rx_reset(UartState *s)
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static void uart_rx_reset(CadenceUARTState *s)
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{
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s->rx_wpos = 0;
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s->rx_count = 0;
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@ -166,12 +169,12 @@ static void uart_rx_reset(UartState *s)
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}
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}
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static void uart_tx_reset(UartState *s)
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static void uart_tx_reset(CadenceUARTState *s)
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{
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s->tx_count = 0;
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}
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static void uart_send_breaks(UartState *s)
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static void uart_send_breaks(CadenceUARTState *s)
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{
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int break_enabled = 1;
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@ -181,7 +184,7 @@ static void uart_send_breaks(UartState *s)
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}
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}
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static void uart_parameters_setup(UartState *s)
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static void uart_parameters_setup(CadenceUARTState *s)
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{
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QEMUSerialSetParams ssp;
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unsigned int baud_rate, packet_size;
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@ -236,20 +239,20 @@ static void uart_parameters_setup(UartState *s)
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static int uart_can_receive(void *opaque)
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{
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UartState *s = (UartState *)opaque;
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int ret = MAX(RX_FIFO_SIZE, TX_FIFO_SIZE);
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CadenceUARTState *s = opaque;
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int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
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uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
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if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
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ret = MIN(ret, RX_FIFO_SIZE - s->rx_count);
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ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
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}
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if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
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ret = MIN(ret, TX_FIFO_SIZE - s->tx_count);
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ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
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}
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return ret;
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}
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static void uart_ctrl_update(UartState *s)
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static void uart_ctrl_update(CadenceUARTState *s)
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{
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if (s->r[R_CR] & UART_CR_TXRST) {
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uart_tx_reset(s);
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@ -268,7 +271,7 @@ static void uart_ctrl_update(UartState *s)
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static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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int i;
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@ -276,12 +279,12 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
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return;
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}
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if (s->rx_count == RX_FIFO_SIZE) {
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if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
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s->r[R_CISR] |= UART_INTR_ROVR;
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} else {
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for (i = 0; i < size; i++) {
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s->rx_fifo[s->rx_wpos] = buf[i];
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s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
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s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
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s->rx_count++;
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}
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timer_mod(s->fifo_trigger_handle, new_rx_time +
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@ -293,7 +296,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
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static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
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void *opaque)
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{
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UartState *s = opaque;
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CadenceUARTState *s = opaque;
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int ret;
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/* instant drain the fifo when there's no back-end */
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@ -320,14 +323,15 @@ static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
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return FALSE;
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}
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static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
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static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
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int size)
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{
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if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
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return;
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}
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if (size > TX_FIFO_SIZE - s->tx_count) {
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size = TX_FIFO_SIZE - s->tx_count;
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if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
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size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
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/*
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* This can only be a guest error via a bad tx fifo register push,
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* as can_receive() should stop remote loop and echo modes ever getting
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@ -345,7 +349,7 @@ static void uart_write_tx_fifo(UartState *s, const uint8_t *buf, int size)
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static void uart_receive(void *opaque, const uint8_t *buf, int size)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
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if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
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@ -358,7 +362,7 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
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static void uart_event(void *opaque, int event)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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uint8_t buf = '\0';
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if (event == CHR_EVENT_BREAK) {
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@ -368,15 +372,15 @@ static void uart_event(void *opaque, int event)
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uart_update_status(s);
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}
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static void uart_read_rx_fifo(UartState *s, uint32_t *c)
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static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
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{
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if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
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return;
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}
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if (s->rx_count) {
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uint32_t rx_rpos =
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(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
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uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
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s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
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*c = s->rx_fifo[rx_rpos];
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s->rx_count--;
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@ -393,7 +397,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
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static void uart_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
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offset >>= 2;
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@ -437,11 +441,11 @@ static void uart_write(void *opaque, hwaddr offset,
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static uint64_t uart_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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UartState *s = (UartState *)opaque;
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CadenceUARTState *s = opaque;
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uint32_t c = 0;
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offset >>= 2;
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if (offset >= R_MAX) {
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if (offset >= CADENCE_UART_R_MAX) {
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c = 0;
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} else if (offset == R_TX_RX) {
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uart_read_rx_fifo(s, &c);
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@ -461,7 +465,7 @@ static const MemoryRegionOps uart_ops = {
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static void cadence_uart_reset(DeviceState *dev)
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{
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UartState *s = CADENCE_UART(dev);
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CadenceUARTState *s = CADENCE_UART(dev);
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s->r[R_CR] = 0x00000128;
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s->r[R_IMR] = 0;
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@ -478,7 +482,7 @@ static void cadence_uart_reset(DeviceState *dev)
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static void cadence_uart_realize(DeviceState *dev, Error **errp)
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{
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UartState *s = CADENCE_UART(dev);
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CadenceUARTState *s = CADENCE_UART(dev);
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s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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fifo_trigger_update, s);
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@ -495,7 +499,7 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)
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static void cadence_uart_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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UartState *s = CADENCE_UART(obj);
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CadenceUARTState *s = CADENCE_UART(obj);
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memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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@ -506,7 +510,7 @@ static void cadence_uart_init(Object *obj)
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static int cadence_uart_post_load(void *opaque, int version_id)
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{
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UartState *s = opaque;
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CadenceUARTState *s = opaque;
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uart_parameters_setup(s);
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uart_update_status(s);
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@ -519,13 +523,15 @@ static const VMStateDescription vmstate_cadence_uart = {
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.minimum_version_id = 2,
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.post_load = cadence_uart_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
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VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
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VMSTATE_UINT8_ARRAY(tx_fifo, UartState, RX_FIFO_SIZE),
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VMSTATE_UINT32(rx_count, UartState),
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VMSTATE_UINT32(tx_count, UartState),
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VMSTATE_UINT32(rx_wpos, UartState),
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VMSTATE_TIMER_PTR(fifo_trigger_handle, UartState),
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VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
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VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
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CADENCE_UART_RX_FIFO_SIZE),
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VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
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CADENCE_UART_TX_FIFO_SIZE),
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VMSTATE_UINT32(rx_count, CadenceUARTState),
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VMSTATE_UINT32(tx_count, CadenceUARTState),
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VMSTATE_UINT32(rx_wpos, CadenceUARTState),
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VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -544,7 +550,7 @@ static void cadence_uart_class_init(ObjectClass *klass, void *data)
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static const TypeInfo cadence_uart_info = {
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.name = TYPE_CADENCE_UART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(UartState),
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.instance_size = sizeof(CadenceUARTState),
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.instance_init = cadence_uart_init,
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.class_init = cadence_uart_class_init,
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};
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