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Desambiguate pflash_register().

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pflash_t is still ambiguous... perhaps both emulations should sit in a single file.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3794 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-12-10 00:28:27 +00:00
parent 52fc1d83bc
commit 88eeee0a31
6 changed files with 38 additions and 29 deletions
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19
hw/flash.h
View File

@ -1,11 +1,19 @@
/* NOR flash devices */ /* NOR flash devices */
typedef struct pflash_t pflash_t; typedef struct pflash_t pflash_t;
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, /* pflash_cfi01.c */
BlockDriverState *bs, pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
uint32_t sector_len, int nb_blocs, int width, BlockDriverState *bs,
uint16_t id0, uint16_t id1, uint32_t sector_len, int nb_blocs, int width,
uint16_t id2, uint16_t id3); uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3);
/* nand.c */ /* nand.c */
struct nand_flash_s; struct nand_flash_s;
@ -37,4 +45,3 @@ uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
void ecc_reset(struct ecc_state_s *s); void ecc_reset(struct ecc_state_s *s);
void ecc_put(QEMUFile *f, struct ecc_state_s *s); void ecc_put(QEMUFile *f, struct ecc_state_s *s);
void ecc_get(QEMUFile *f, struct ecc_state_s *s); void ecc_get(QEMUFile *f, struct ecc_state_s *s);

4
hw/gumstix.c
View File

@ -67,7 +67,7 @@ static void connex_init(int ram_size, int vga_ram_size,
exit(1); exit(1);
} }
if (!pflash_register(0x00000000, qemu_ram_alloc(connex_rom), if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(connex_rom),
drives_table[index].bdrv, sector_len, connex_rom / sector_len, drives_table[index].bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0)) { 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
@ -107,7 +107,7 @@ static void verdex_init(int ram_size, int vga_ram_size,
exit(1); exit(1);
} }
if (!pflash_register(0x00000000, qemu_ram_alloc(verdex_rom), if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(verdex_rom),
drives_table[index].bdrv, sector_len, verdex_rom / sector_len, drives_table[index].bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0)) { 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");

6
hw/mainstone.c
View File

@ -55,7 +55,8 @@ static void mainstone_common_init(int ram_size, int vga_ram_size,
"'pflash' parameter\n"); "'pflash' parameter\n");
exit(1); exit(1);
} }
if (!pflash_register(MST_FLASH_0, mainstone_ram + PXA2XX_INTERNAL_SIZE, if (!pflash_cfi01_register(MST_FLASH_0,
mainstone_ram + PXA2XX_INTERNAL_SIZE,
drives_table[index].bdrv, drives_table[index].bdrv,
256 * 1024, 128, 4, 0, 0, 0, 0)) { 256 * 1024, 128, 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
@ -68,7 +69,8 @@ static void mainstone_common_init(int ram_size, int vga_ram_size,
"'pflash' parameter\n"); "'pflash' parameter\n");
exit(1); exit(1);
} }
if (!pflash_register(MST_FLASH_1, mainstone_ram + PXA2XX_INTERNAL_SIZE, if (!pflash_cfi01_register(MST_FLASH_1,
mainstone_ram + PXA2XX_INTERNAL_SIZE,
drives_table[index].bdrv, drives_table[index].bdrv,
256 * 1024, 128, 4, 0, 0, 0, 0)) { 256 * 1024, 128, 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");

10
hw/pflash_cfi01.c
View File

@ -483,11 +483,11 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, BlockDriverState *bs, target_ulong sector_len,
target_ulong sector_len, int nb_blocs, int width, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3) uint16_t id2, uint16_t id3)
{ {
pflash_t *pfl; pflash_t *pfl;
target_long total_len; target_long total_len;

10
hw/pflash_cfi02.c
View File

@ -524,11 +524,11 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
BlockDriverState *bs, BlockDriverState *bs, target_ulong sector_len,
uint32_t sector_len, int nb_blocs, int width, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3) uint16_t id2, uint16_t id3)
{ {
pflash_t *pfl; pflash_t *pfl;
int32_t total_len; int32_t total_len;

18
hw/ppc405_boards.c
View File

@ -234,9 +234,9 @@ static void ref405ep_init (int ram_size, int vga_ram_size,
fl_idx, bios_size, bios_offset, -bios_size, fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
#endif #endif
pflash_register((uint32_t)(-bios_size), bios_offset, pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
drives_table[index].bdrv, 65536, fl_sectors, 2, drives_table[index].bdrv, 65536, fl_sectors, 2,
0x0001, 0x22DA, 0x0000, 0x0000); 0x0001, 0x22DA, 0x0000, 0x0000);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -551,9 +551,9 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size,
fl_idx, bios_size, bios_offset, -bios_size, fl_idx, bios_size, bios_offset, -bios_size,
bdrv_get_device_name(drives_table[index].bdrv), fl_sectors); bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
#endif #endif
pflash_register((uint32_t)(-bios_size), bios_offset, pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
drives_table[index].bdrv, 65536, fl_sectors, 4, drives_table[index].bdrv, 65536, fl_sectors, 4,
0x0001, 0x22DA, 0x0000, 0x0000); 0x0001, 0x22DA, 0x0000, 0x0000);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -587,9 +587,9 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size,
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
bdrv_get_device_name(drives_table[index].bdrv)); bdrv_get_device_name(drives_table[index].bdrv));
#endif #endif
pflash_register(0xfc000000, bios_offset, drives_table[index].bdrv, pflash_cfi02_register(0xfc000000, bios_offset,
65536, fl_sectors, 4, drives_table[index].bdrv, 65536, fl_sectors, 4,
0x0001, 0x22DA, 0x0000, 0x0000); 0x0001, 0x22DA, 0x0000, 0x0000);
fl_idx++; fl_idx++;
} }
/* Register CLPD & LCD display */ /* Register CLPD & LCD display */