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target/ppc: Make divw[u] handler method decodetree compatible.

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The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it decodetree compatible, so that the
mentioned insns can be safely move to decodetree specs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Chinmay Rath 2024-04-23 12:02:28 +05:30 committed by Nicholas Piggin
parent a1faff873a
commit 86e6202a57
1 changed files with 5 additions and 4 deletions
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9
target/ppc/translate.c
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@ -1737,8 +1737,9 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
}
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
TCGv arg2, int sign, int compute_ov)
static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret,
TCGv arg1, TCGv arg2, bool sign,
bool compute_ov, bool compute_rc0)
{
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
@ -1772,7 +1773,7 @@ static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
if (unlikely(compute_rc0)) {
gen_set_Rc0(ctx, ret);
}
}
@ -1782,7 +1783,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
{ \
gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
sign, compute_ov); \
sign, compute_ov, Rc(ctx->opcode)); \
}
/* divwu divwu. divwuo divwuo. */
GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);