tcg-aarch64: Define TCG_TARGET_INSN_UNIT_SIZE
And use tcg pointer differencing functions as appropriate. Acked-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
267c931985
commit
8587c30c3e
@ -63,40 +63,34 @@ static const int tcg_target_call_oarg_regs[1] = {
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# endif
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#endif
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static inline void reloc_pc26(void *code_ptr, intptr_t target)
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static inline void reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
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{
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intptr_t offset = (target - (intptr_t)code_ptr) / 4;
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ptrdiff_t offset = target - code_ptr;
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assert(offset == sextract64(offset, 0, 26));
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/* read instruction, mask away previous PC_REL26 parameter contents,
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set the proper offset, then write back the instruction. */
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uint32_t insn = *(uint32_t *)code_ptr;
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insn = deposit32(insn, 0, 26, offset);
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*(uint32_t *)code_ptr = insn;
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*code_ptr = deposit32(*code_ptr, 0, 26, offset);
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}
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static inline void reloc_pc19(void *code_ptr, intptr_t target)
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static inline void reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
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{
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intptr_t offset = (target - (intptr_t)code_ptr) / 4;
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/* read instruction, mask away previous PC_REL19 parameter contents,
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set the proper offset, then write back the instruction. */
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uint32_t insn = *(uint32_t *)code_ptr;
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insn = deposit32(insn, 5, 19, offset);
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*(uint32_t *)code_ptr = insn;
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ptrdiff_t offset = target - code_ptr;
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assert(offset == sextract64(offset, 0, 19));
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*code_ptr = deposit32(*code_ptr, 5, 19, offset);
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}
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static inline void patch_reloc(uint8_t *code_ptr, int type,
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static inline void patch_reloc(tcg_insn_unit *code_ptr, int type,
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intptr_t value, intptr_t addend)
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{
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value += addend;
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assert(addend == 0);
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switch (type) {
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case R_AARCH64_JUMP26:
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case R_AARCH64_CALL26:
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reloc_pc26(code_ptr, value);
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reloc_pc26(code_ptr, (tcg_insn_unit *)value);
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break;
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case R_AARCH64_CONDBR19:
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reloc_pc19(code_ptr, value);
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reloc_pc19(code_ptr, (tcg_insn_unit *)value);
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break;
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default:
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tcg_abort();
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}
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@ -794,15 +788,10 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
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}
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}
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static inline void tcg_out_goto(TCGContext *s, intptr_t target)
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static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
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{
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intptr_t offset = (target - (intptr_t)s->code_ptr) / 4;
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if (offset < -0x02000000 || offset >= 0x02000000) {
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/* out of 26bit range */
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tcg_abort();
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}
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ptrdiff_t offset = target - s->code_ptr;
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assert(offset == sextract64(offset, 0, 26));
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tcg_out_insn(s, 3206, B, offset);
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}
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@ -828,29 +817,23 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg)
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tcg_out_insn(s, 3207, BLR, reg);
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}
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static inline void tcg_out_call(TCGContext *s, intptr_t target)
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static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
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{
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intptr_t offset = (target - (intptr_t)s->code_ptr) / 4;
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if (offset < -0x02000000 || offset >= 0x02000000) { /* out of 26bit rng */
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, target);
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tcg_out_callr(s, TCG_REG_TMP);
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} else {
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ptrdiff_t offset = target - s->code_ptr;
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if (offset == sextract64(offset, 0, 26)) {
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tcg_out_insn(s, 3206, BL, offset);
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} else {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, (intptr_t)target);
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tcg_out_callr(s, TCG_REG_TMP);
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}
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}
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void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
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{
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intptr_t target = addr;
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intptr_t offset = (target - (intptr_t)jmp_addr) / 4;
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tcg_insn_unit *code_ptr = (tcg_insn_unit *)jmp_addr;
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tcg_insn_unit *target = (tcg_insn_unit *)addr;
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if (offset < -0x02000000 || offset >= 0x02000000) {
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/* out of 26bit range */
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tcg_abort();
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}
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patch_reloc((uint8_t *)jmp_addr, R_AARCH64_JUMP26, target, 0);
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reloc_pc26(code_ptr, target);
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flush_icache_range(jmp_addr, jmp_addr + 4);
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}
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@ -862,7 +845,7 @@ static inline void tcg_out_goto_label(TCGContext *s, int label_index)
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tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, label_index, 0);
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tcg_out_goto_noaddr(s);
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} else {
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tcg_out_goto(s, l->u.value);
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tcg_out_goto(s, l->u.value_ptr);
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}
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}
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@ -884,9 +867,8 @@ static void tcg_out_brcond(TCGContext *s, TCGMemOp ext, TCGCond c, TCGArg a,
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tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, label, 0);
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offset = tcg_in32(s) >> 5;
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} else {
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offset = l->u.value - (uintptr_t)s->code_ptr;
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offset >>= 2;
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assert(offset >= -0x40000 && offset < 0x40000);
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offset = l->u.value_ptr - s->code_ptr;
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assert(offset == sextract64(offset, 0, 19));
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}
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if (need_cmp) {
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@ -982,7 +964,7 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_ld_helpers[16] = {
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static void * const qemu_ld_helpers[16] = {
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[MO_UB] = helper_ret_ldub_mmu,
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[MO_LEUW] = helper_le_lduw_mmu,
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[MO_LEUL] = helper_le_ldul_mmu,
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@ -995,7 +977,7 @@ static const void * const qemu_ld_helpers[16] = {
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/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
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* uintxx_t val, int mmu_idx, uintptr_t ra)
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*/
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static const void * const qemu_st_helpers[16] = {
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static void * const qemu_st_helpers[16] = {
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[MO_UB] = helper_ret_stb_mmu,
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[MO_LEUW] = helper_le_stw_mmu,
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[MO_LEUL] = helper_le_stl_mmu,
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@ -1005,11 +987,11 @@ static const void * const qemu_st_helpers[16] = {
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[MO_BEQ] = helper_be_stq_mmu,
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};
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static inline void tcg_out_adr(TCGContext *s, TCGReg rd, uintptr_t addr)
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static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
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{
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addr -= (uintptr_t)s->code_ptr;
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assert(addr == sextract64(addr, 0, 21));
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tcg_out_insn(s, 3406, ADR, rd, addr);
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ptrdiff_t offset = tcg_pcrel_diff(s, target);
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assert(offset == sextract64(offset, 0, 21));
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tcg_out_insn(s, 3406, ADR, rd, offset);
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}
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static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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@ -1017,20 +999,20 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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TCGMemOp opc = lb->opc;
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TCGMemOp size = opc & MO_SIZE;
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reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr);
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reloc_pc19(lb->label_ptr[0], s->code_ptr);
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tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
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tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
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tcg_out_adr(s, TCG_REG_X3, (intptr_t)lb->raddr);
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tcg_out_call(s, (intptr_t)qemu_ld_helpers[opc & ~MO_SIGN]);
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tcg_out_adr(s, TCG_REG_X3, lb->raddr);
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tcg_out_call(s, qemu_ld_helpers[opc & ~MO_SIGN]);
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if (opc & MO_SIGN) {
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tcg_out_sxt(s, TCG_TYPE_I64, size, lb->datalo_reg, TCG_REG_X0);
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} else {
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tcg_out_mov(s, size == MO_64, lb->datalo_reg, TCG_REG_X0);
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}
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tcg_out_goto(s, (intptr_t)lb->raddr);
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tcg_out_goto(s, lb->raddr);
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}
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static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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@ -1038,21 +1020,21 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
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TCGMemOp opc = lb->opc;
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TCGMemOp size = opc & MO_SIZE;
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reloc_pc19(lb->label_ptr[0], (intptr_t)s->code_ptr);
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reloc_pc19(lb->label_ptr[0], s->code_ptr);
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tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_X0, TCG_AREG0);
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tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
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tcg_out_mov(s, size == MO_64, TCG_REG_X2, lb->datalo_reg);
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tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
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tcg_out_adr(s, TCG_REG_X4, (intptr_t)lb->raddr);
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tcg_out_call(s, (intptr_t)qemu_st_helpers[opc]);
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tcg_out_goto(s, (intptr_t)lb->raddr);
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tcg_out_adr(s, TCG_REG_X4, lb->raddr);
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tcg_out_call(s, qemu_st_helpers[opc]);
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tcg_out_goto(s, lb->raddr);
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}
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static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
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TCGReg data_reg, TCGReg addr_reg,
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int mem_index,
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uint8_t *raddr, uint8_t *label_ptr)
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int mem_index, tcg_insn_unit *raddr,
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tcg_insn_unit *label_ptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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@ -1070,7 +1052,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
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the slow path. Generated code returns the host addend in X1,
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clobbers X0,X2,X3,TMP. */
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static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp s_bits,
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uint8_t **label_ptr, int mem_index, bool is_read)
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tcg_insn_unit **label_ptr, int mem_index,
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bool is_read)
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{
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TCGReg base = TCG_AREG0;
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int tlb_offset = is_read ?
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@ -1218,7 +1201,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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{
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#ifdef CONFIG_SOFTMMU
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TCGMemOp s_bits = memop & MO_SIZE;
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uint8_t *label_ptr;
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tcg_insn_unit *label_ptr;
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tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1);
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tcg_out_qemu_ld_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);
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@ -1235,7 +1218,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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{
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#ifdef CONFIG_SOFTMMU
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TCGMemOp s_bits = memop & MO_SIZE;
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uint8_t *label_ptr;
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tcg_insn_unit *label_ptr;
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tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0);
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tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);
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@ -1247,7 +1230,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
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#endif /* CONFIG_SOFTMMU */
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}
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static uint8_t *tb_ret_addr;
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static tcg_insn_unit *tb_ret_addr;
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static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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const TCGArg args[TCG_MAX_OP_ARGS],
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@ -1270,7 +1253,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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switch (opc) {
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case INDEX_op_exit_tb:
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
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tcg_out_goto(s, (intptr_t)tb_ret_addr);
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tcg_out_goto(s, tb_ret_addr);
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break;
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case INDEX_op_goto_tb:
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@ -1278,16 +1261,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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#error "USE_DIRECT_JUMP required for aarch64"
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#endif
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assert(s->tb_jmp_offset != NULL); /* consistency for USE_DIRECT_JUMP */
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s->tb_jmp_offset[a0] = s->code_ptr - s->code_buf;
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s->tb_jmp_offset[a0] = tcg_current_code_size(s);
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/* actual branch destination will be patched by
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aarch64_tb_set_jmp_target later, beware retranslation. */
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tcg_out_goto_noaddr(s);
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s->tb_next_offset[a0] = s->code_ptr - s->code_buf;
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s->tb_next_offset[a0] = tcg_current_code_size(s);
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break;
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case INDEX_op_call:
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if (const_args[0]) {
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tcg_out_call(s, a0);
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tcg_out_call(s, (tcg_insn_unit *)(intptr_t)a0);
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} else {
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tcg_out_callr(s, a0);
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}
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@ -13,6 +13,7 @@
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#ifndef TCG_TARGET_AARCH64
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#define TCG_TARGET_AARCH64 1
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#undef TCG_TARGET_STACK_GROWSUP
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typedef enum {
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