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target/i386: Fix carry flag for BLSI

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BLSI has inverted semantics for C as compared to the other two
BMI1 instructions, BLSMSK and BLSR.  Introduce CC_OP_BLSI* for
this purpose.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2175
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20240801075845.573075-3-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-01 17:57:45 +10:00
parent 266d6dddbd
commit 83a3a20e59
7 changed files with 72 additions and 1 deletions
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5
target/i386/cpu.h
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@ -1339,6 +1339,11 @@ typedef enum {
CC_OP_BMILGL,
CC_OP_BMILGQ,
CC_OP_BLSIB, /* Z,S via CC_DST, C = SRC!=0; O=0; P,A undefined */
CC_OP_BLSIW,
CC_OP_BLSIL,
CC_OP_BLSIQ,
/*
* Note that only CC_OP_POPCNT (i.e. the one with MO_TL size)
* is used or implemented, because the translation needs

18
target/i386/tcg/cc_helper.c
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@ -186,6 +186,13 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
case CC_OP_BMILGL:
return compute_all_bmilgl(dst, src1);
case CC_OP_BLSIB:
return compute_all_blsib(dst, src1);
case CC_OP_BLSIW:
return compute_all_blsiw(dst, src1);
case CC_OP_BLSIL:
return compute_all_blsil(dst, src1);
case CC_OP_ADCX:
return compute_all_adcx(dst, src1, src2);
case CC_OP_ADOX:
@ -216,6 +223,8 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
return compute_all_sarq(dst, src1);
case CC_OP_BMILGQ:
return compute_all_bmilgq(dst, src1);
case CC_OP_BLSIQ:
return compute_all_blsiq(dst, src1);
#endif
}
}
@ -308,6 +317,13 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
case CC_OP_BMILGL:
return compute_c_bmilgl(dst, src1);
case CC_OP_BLSIB:
return compute_c_blsib(dst, src1);
case CC_OP_BLSIW:
return compute_c_blsiw(dst, src1);
case CC_OP_BLSIL:
return compute_c_blsil(dst, src1);
#ifdef TARGET_X86_64
case CC_OP_ADDQ:
return compute_c_addq(dst, src1);
@ -321,6 +337,8 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
return compute_c_shlq(dst, src1);
case CC_OP_BMILGQ:
return compute_c_bmilgq(dst, src1);
case CC_OP_BLSIQ:
return compute_c_blsiq(dst, src1);
#endif
}
}

18
target/i386/tcg/cc_helper_template.h.inc
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@ -235,6 +235,24 @@ static int glue(compute_c_bmilg, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
return src1 == 0;
}
static int glue(compute_all_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
int cf, pf, af, zf, sf, of;
cf = (src1 != 0);
pf = 0; /* undefined */
af = 0; /* undefined */
zf = (dst == 0) * CC_Z;
sf = lshift(dst, 8 - DATA_BITS) & CC_S;
of = 0;
return cf | pf | af | zf | sf | of;
}
static int glue(compute_c_blsi, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1)
{
return src1 != 0;
}
#undef DATA_BITS
#undef SIGN_MASK
#undef DATA_TYPE

2
target/i386/tcg/emit.c.inc
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@ -1304,7 +1304,7 @@ static void gen_BLSI(DisasContext *s, X86DecodedInsn *decode)
/* input in T1, which is ready for prepare_update2_cc */
tcg_gen_neg_tl(s->T0, s->T1);
tcg_gen_and_tl(s->T0, s->T0, s->T1);
prepare_update2_cc(decode, s, CC_OP_BMILGB + ot);
prepare_update2_cc(decode, s, CC_OP_BLSIB + ot);
}
static void gen_BLSMSK(DisasContext *s, X86DecodedInsn *decode)

5
target/i386/tcg/translate.c
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@ -304,6 +304,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = {
[CC_OP_SHLB ... CC_OP_SHLQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_SARB ... CC_OP_SARQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BMILGB ... CC_OP_BMILGQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_BLSIB ... CC_OP_BLSIQ] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADCX] = USES_CC_DST | USES_CC_SRC,
[CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2,
[CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2,
@ -922,6 +923,10 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
size = s->cc_op - CC_OP_BMILGB;
return gen_prepare_val_nz(cpu_cc_src, size, true);
case CC_OP_BLSIB ... CC_OP_BLSIQ:
size = s->cc_op - CC_OP_BLSIB;
return gen_prepare_val_nz(cpu_cc_src, size, false);
case CC_OP_ADCX:
case CC_OP_ADCOX:
return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst,

1
tests/tcg/x86_64/Makefile.target
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@ -16,6 +16,7 @@ X86_64_TESTS += noexec
X86_64_TESTS += cmpxchg
X86_64_TESTS += adox
X86_64_TESTS += test-1648
X86_64_TESTS += test-2175
TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64
else
TESTS=$(MULTIARCH_TESTS)

24
tests/tcg/x86_64/test-2175.c Normal file
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@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* See https://gitlab.com/qemu-project/qemu/-/issues/2185 */
#include <assert.h>
int test_setc(unsigned int x, unsigned int y)
{
asm("blsi %1, %0; setc %b0" : "+r"(x) : "r"(y));
return (unsigned char)x;
}
int test_pushf(unsigned int x, unsigned int y)
{
asm("blsi %1, %0; pushf; pop %q0" : "+r"(x) : "r"(y));
return x & 1;
}
int main()
{
assert(test_setc(1, 0xedbf530a));
assert(test_pushf(1, 0xedbf530a));
return 0;
}