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target/i386: Split out gen_prepare_val_nz

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Split out the TCG_COND_TSTEQ logic from gen_prepare_eflags_z,
and use it for CC_OP_BMILG* as well.  Prepare for requiring
both zero and non-zero senses.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240801075845.573075-2-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-01 17:42:36 +10:00
parent 5b73b248a1
commit 266d6dddbd
1 changed files with 14 additions and 8 deletions
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22
target/i386/tcg/translate.c
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@ -865,6 +865,18 @@ static CCPrepare gen_prepare_sign_nz(TCGv src, MemOp size)
}
}
static CCPrepare gen_prepare_val_nz(TCGv src, MemOp size, bool eqz)
{
if (size == MO_TL) {
return (CCPrepare) { .cond = eqz ? TCG_COND_EQ : TCG_COND_NE,
.reg = src };
} else {
return (CCPrepare) { .cond = eqz ? TCG_COND_TSTEQ : TCG_COND_TSTNE,
.imm = MAKE_64BIT_MASK(0, 8 << size),
.reg = src };
}
}
/* compute eflags.C, trying to store it in reg if not NULL */
static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
{
@ -908,8 +920,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg)
case CC_OP_BMILGB ... CC_OP_BMILGQ:
size = s->cc_op - CC_OP_BMILGB;
gen_ext_tl(cpu_cc_src, cpu_cc_src, size, false);
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_src };
return gen_prepare_val_nz(cpu_cc_src, size, true);
case CC_OP_ADCX:
case CC_OP_ADCOX:
@ -1006,12 +1017,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg)
default:
{
MemOp size = (s->cc_op - CC_OP_ADDB) & 3;
if (size == MO_TL) {
return (CCPrepare) { .cond = TCG_COND_EQ, .reg = cpu_cc_dst };
} else {
return (CCPrepare) { .cond = TCG_COND_TSTEQ, .reg = cpu_cc_dst,
.imm = (1ull << (8 << size)) - 1 };
}
return gen_prepare_val_nz(cpu_cc_dst, size, true);
}
}
}