target/riscv: The whole vector register move instructions depend on vsew
The RISC-V v spec 16.6 section says that the whole vector register move instructions operate as if EEW=SEW. So it should depends on the vsew field of vtype register. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231129170400.21251-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
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QEMU_IS_ALIGNED(a->rs2, LEN)) { \
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uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
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if (s->vstart_eq_zero) { \
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/* EEW = 8 */ \
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tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
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tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
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vreg_ofs(s, a->rs2), maxsz, maxsz); \
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mark_vs_dirty(s); \
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} else { \
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