From 79fc6d38a819cd30e578023a231385f63583eafb Mon Sep 17 00:00:00 2001 From: Max Chou Date: Thu, 30 Nov 2023 01:03:58 +0800 Subject: [PATCH] target/riscv: The whole vector register move instructions depend on vsew The RISC-V v spec 16.6 section says that the whole vector register move instructions operate as if EEW=SEW. So it should depends on the vsew field of vtype register. Signed-off-by: Max Chou Acked-by: Richard Henderson Message-ID: <20231129170400.21251-3-max.chou@sifive.com> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 114ad87397..3871f0ea73 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ QEMU_IS_ALIGNED(a->rs2, LEN)) { \ uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \ if (s->vstart_eq_zero) { \ - /* EEW = 8 */ \ - tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \ + tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \ vreg_ofs(s, a->rs2), maxsz, maxsz); \ mark_vs_dirty(s); \ } else { \