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tcg: Rename debug_insn_start to insn_start

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With an eye toward making it mandatory.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2015-08-29 12:37:33 -07:00
parent 5fdb4671b0
commit 765b842ade
23 changed files with 28 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target-alpha/translate.c
View File

@ -2940,7 +2940,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
num_insns++;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.pc);
tcg_gen_insn_start(ctx.pc);
}
TCGV_UNUSED_I64(ctx.zero);

2
target-arm/translate-a64.c
View File

@ -11109,7 +11109,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
if (dc->ss_active && !dc->pstate_ss) {

2
target-arm/translate.c
View File

@ -11353,7 +11353,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
gen_io_start();
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
if (dc->ss_active && !dc->pstate_ss) {

4
target-cris/translate.c
View File

@ -2995,8 +2995,8 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
int i;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
}
tcg_gen_insn_start(dc->pc);
}
/* Load a halfword onto the instruction register. */
dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);

2
target-cris/translate_v10.c
View File

@ -1200,7 +1200,7 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
unsigned int insn_len = 2;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
/* Load a halfword onto the instruction register. */
dc->ir = cpu_lduw_code(env, dc->pc);

2
target-i386/translate.c
View File

@ -4402,7 +4402,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
int rex_w, rex_r;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(pc_start);
tcg_gen_insn_start(pc_start);
}
s->pc = pc_start;
prefixes = 0;

2
target-lm32/translate.c
View File

@ -1006,7 +1006,7 @@ static const DecoderInfo decinfo[] = {
static inline void decode(DisasContext *dc, uint32_t ir)
{
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
dc->ir = ir;

2
target-m68k/translate.c
View File

@ -2956,7 +2956,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
uint16_t insn;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(s->pc);
tcg_gen_insn_start(s->pc);
}
insn = cpu_lduw_code(env, s->pc);

2
target-microblaze/translate.c
View File

@ -1589,7 +1589,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
int i;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
dc->ir = ir;

2
target-mips/translate.c
View File

@ -18905,7 +18905,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx->pc);
tcg_gen_insn_start(ctx->pc);
}
op = MASK_OP_MAJOR(ctx->opcode);

2
target-moxie/translate.c
View File

@ -154,7 +154,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
int length = 2;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx->pc);
tcg_gen_insn_start(ctx->pc);
}
/* Examine the 16-bit opcode. */

2
target-openrisc/translate.c
View File

@ -1689,7 +1689,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {

2
target-ppc/translate.c
View File

@ -11516,7 +11516,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx.nip);
tcg_gen_insn_start(ctx.nip);
}
ctx.nip += 4;
table = env->opcodes;

2
target-s390x/translate.c
View File

@ -5375,7 +5375,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc.pc);
tcg_gen_insn_start(dc.pc);
}
status = NO_EXIT;

2
target-sh4/translate.c
View File

@ -1791,7 +1791,7 @@ static void decode_opc(DisasContext * ctx)
uint32_t old_flags = ctx->flags;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(ctx->pc);
tcg_gen_insn_start(ctx->pc);
}
_decode_opc(ctx);

2
target-sparc/translate.c
View File

@ -2483,7 +2483,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
target_long simm;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
opc = GET_FIELD(insn, 0, 1);

2
target-tilegx/translate.c
View File

@ -2009,7 +2009,7 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
dc->num_wb = 0;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc->pc);
tcg_gen_insn_start(dc->pc);
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, " %" PRIx64 ": { ", dc->pc);

2
target-unicore32/translate.c
View File

@ -1795,7 +1795,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
unsigned int insn;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(s->pc);
tcg_gen_insn_start(s->pc);
}
insn = cpu_ldl_code(env, s->pc);

2
target-xtensa/translate.c
View File

@ -3078,7 +3078,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
}
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
tcg_gen_debug_insn_start(dc.pc);
tcg_gen_insn_start(dc.pc);
}
++dc.ccount_delta;

6
tcg/tcg-op.h
View File

@ -701,14 +701,14 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
#endif
/* debug info: write the PC of the corresponding QEMU CPU instruction */
static inline void tcg_gen_debug_insn_start(uint64_t pc)
static inline void tcg_gen_insn_start(uint64_t pc)
{
/* XXX: must really use a 32 bit size for TCGArg in all cases */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
tcg_gen_op2ii(INDEX_op_debug_insn_start,
tcg_gen_op2ii(INDEX_op_insn_start,
(uint32_t)(pc), (uint32_t)(pc >> 32));
#else
tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
tcg_gen_op1i(INDEX_op_insn_start, pc);
#endif
}

4
tcg/tcg-opc.h
View File

@ -175,9 +175,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
/* QEMU specific */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
DEF(insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
#else
DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
#endif
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)

6
tcg/tcg.c
View File

@ -990,7 +990,7 @@ void tcg_dump_ops(TCGContext *s)
def = &tcg_op_defs[c];
args = &s->gen_opparam_buf[op->args];
if (c == INDEX_op_debug_insn_start) {
if (c == INDEX_op_insn_start) {
uint64_t pc;
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
pc = ((uint64_t)args[1] << 32) | args[0];
@ -1400,7 +1400,7 @@ static void tcg_liveness_analysis(TCGContext *s)
}
}
break;
case INDEX_op_debug_insn_start:
case INDEX_op_insn_start:
break;
case INDEX_op_discard:
/* mark the temporary as dead */
@ -2359,7 +2359,7 @@ static inline int tcg_gen_code_common(TCGContext *s,
case INDEX_op_movi_i64:
tcg_reg_alloc_movi(s, args, dead_args, sync_args);
break;
case INDEX_op_debug_insn_start:
case INDEX_op_insn_start:
break;
case INDEX_op_discard:
temp_dead(s, args[0]);

9
tci.c
View File

@ -1081,15 +1081,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
/* QEMU specific operations. */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
case INDEX_op_debug_insn_start:
TODO();
break;
#else
case INDEX_op_debug_insn_start:
TODO();
break;
#endif
case INDEX_op_exit_tb:
next_tb = *(uint64_t *)tb_ptr;
goto exit;