diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 2ba5fb80ae..76916f434a 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -2940,7 +2940,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
         num_insns++;
 
 	if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(ctx.pc);
+            tcg_gen_insn_start(ctx.pc);
         }
 
         TCGV_UNUSED_I64(ctx.zero);
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index ec0936cf97..a618711b64 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11109,7 +11109,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
         }
 
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(dc->pc);
+            tcg_gen_insn_start(dc->pc);
         }
 
         if (dc->ss_active && !dc->pstate_ss) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 84a21ace54..b521fc86f8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11353,7 +11353,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
             gen_io_start();
 
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(dc->pc);
+            tcg_gen_insn_start(dc->pc);
         }
 
         if (dc->ss_active && !dc->pstate_ss) {
diff --git a/target-cris/translate.c b/target-cris/translate.c
index d5b54e1ad4..c5a22afa66 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -2995,8 +2995,8 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
     int i;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(dc->pc);
-        }
+        tcg_gen_insn_start(dc->pc);
+    }
 
     /* Load a halfword onto the instruction register.  */
         dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index da0b2caf85..12d7dfc45e 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1200,7 +1200,7 @@ static unsigned int crisv10_decoder(CPUCRISState *env, DisasContext *dc)
     unsigned int insn_len = 2;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
-        tcg_gen_debug_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc);
 
     /* Load a halfword onto the instruction register.  */
     dc->ir = cpu_lduw_code(env, dc->pc);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 8b35de1a1a..c18f82bfd1 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4402,7 +4402,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
     int rex_w, rex_r;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(pc_start);
+        tcg_gen_insn_start(pc_start);
     }
     s->pc = pc_start;
     prefixes = 0;
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index cf7042e3e0..b1b4cbb750 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1006,7 +1006,7 @@ static const DecoderInfo decinfo[] = {
 static inline void decode(DisasContext *dc, uint32_t ir)
 {
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc);
     }
 
     dc->ir = ir;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 3cdf6652aa..e34bf2b8cd 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2956,7 +2956,7 @@ static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
     uint16_t insn;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(s->pc);
+        tcg_gen_insn_start(s->pc);
     }
 
     insn = cpu_lduw_code(env, s->pc);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 3de89440a6..0d340c0e78 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1589,7 +1589,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
     int i;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc);
     }
 
     dc->ir = ir;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 87d495975a..2b3f2b00b1 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -18905,7 +18905,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     }
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(ctx->pc);
+        tcg_gen_insn_start(ctx->pc);
     }
 
     op = MASK_OP_MAJOR(ctx->opcode);
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index cc77366ee7..0bb94a02b8 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -154,7 +154,7 @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
     int length = 2;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(ctx->pc);
+        tcg_gen_insn_start(ctx->pc);
     }
 
     /* Examine the 16-bit opcode.  */
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 473556e14a..727fbba66f 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1689,7 +1689,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
         }
 
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(dc->pc);
+            tcg_gen_insn_start(dc->pc);
         }
 
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c0eed13f98..c46133d9df 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11516,7 +11516,7 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
                     ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
                     opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(ctx.nip);
+            tcg_gen_insn_start(ctx.nip);
         }
         ctx.nip += 4;
         table = env->opcodes;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 2bca33acca..a87d83c79e 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5375,7 +5375,7 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
         }
 
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(dc.pc);
+            tcg_gen_insn_start(dc.pc);
         }
 
         status = NO_EXIT;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 724c0e7106..d9d2c02a39 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1791,7 +1791,7 @@ static void decode_opc(DisasContext * ctx)
     uint32_t old_flags = ctx->flags;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(ctx->pc);
+        tcg_gen_insn_start(ctx->pc);
     }
 
     _decode_opc(ctx);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 4690b4699a..ef17e26253 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2483,7 +2483,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
     target_long simm;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc);
     }
 
     opc = GET_FIELD(insn, 0, 1);
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index e70c3e5ab7..3fb7fc6a21 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -2009,7 +2009,7 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
     dc->num_wb = 0;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc);
     }
 
     qemu_log_mask(CPU_LOG_TB_IN_ASM, "  %" PRIx64 ":  { ", dc->pc);
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 2fc78e6f3e..63a5192b59 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1795,7 +1795,7 @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
     unsigned int insn;
 
     if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-        tcg_gen_debug_insn_start(s->pc);
+        tcg_gen_insn_start(s->pc);
     }
 
     insn = cpu_ldl_code(env, s->pc);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index a29b3e61bc..ea777dabdd 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -3078,7 +3078,7 @@ void gen_intermediate_code_internal(XtensaCPU *cpu,
         }
 
         if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
-            tcg_gen_debug_insn_start(dc.pc);
+            tcg_gen_insn_start(dc.pc);
         }
 
         ++dc.ccount_delta;
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 6da083a1e9..6409db8893 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -701,14 +701,14 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
 #endif
 
 /* debug info: write the PC of the corresponding QEMU CPU instruction */
-static inline void tcg_gen_debug_insn_start(uint64_t pc)
+static inline void tcg_gen_insn_start(uint64_t pc)
 {
     /* XXX: must really use a 32 bit size for TCGArg in all cases */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-    tcg_gen_op2ii(INDEX_op_debug_insn_start,
+    tcg_gen_op2ii(INDEX_op_insn_start,
                   (uint32_t)(pc), (uint32_t)(pc >> 32));
 #else
-    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
+    tcg_gen_op1i(INDEX_op_insn_start, pc);
 #endif
 }
 
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 02bbf30387..f60d3c2d4e 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -175,9 +175,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
 
 /* QEMU specific */
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
+DEF(insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
 #else
-DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
+DEF(insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
 #endif
 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a2cb027a14..df8788bac5 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -990,7 +990,7 @@ void tcg_dump_ops(TCGContext *s)
         def = &tcg_op_defs[c];
         args = &s->gen_opparam_buf[op->args];
 
-        if (c == INDEX_op_debug_insn_start) {
+        if (c == INDEX_op_insn_start) {
             uint64_t pc;
 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
             pc = ((uint64_t)args[1] << 32) | args[0];
@@ -1400,7 +1400,7 @@ static void tcg_liveness_analysis(TCGContext *s)
                 }
             }
             break;
-        case INDEX_op_debug_insn_start:
+        case INDEX_op_insn_start:
             break;
         case INDEX_op_discard:
             /* mark the temporary as dead */
@@ -2359,7 +2359,7 @@ static inline int tcg_gen_code_common(TCGContext *s,
         case INDEX_op_movi_i64:
             tcg_reg_alloc_movi(s, args, dead_args, sync_args);
             break;
-        case INDEX_op_debug_insn_start:
+        case INDEX_op_insn_start:
             break;
         case INDEX_op_discard:
             temp_dead(s, args[0]);
diff --git a/tci.c b/tci.c
index 70eaab25eb..b5ed7b1f7a 100644
--- a/tci.c
+++ b/tci.c
@@ -1081,15 +1081,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
 
             /* QEMU specific operations. */
 
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-        case INDEX_op_debug_insn_start:
-            TODO();
-            break;
-#else
-        case INDEX_op_debug_insn_start:
-            TODO();
-            break;
-#endif
         case INDEX_op_exit_tb:
             next_tb = *(uint64_t *)tb_ptr;
             goto exit;