hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_htif model to hw/char directory. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -1,6 +1,9 @@
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config ESCC
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config ESCC
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bool
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bool
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config HTIF
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bool
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config PARALLEL
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config PARALLEL
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bool
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bool
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default y
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default y
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@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
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softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_usart.c'))
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softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
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softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfsoc_mmuart.c'))
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specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c'))
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specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
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specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.c'))
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specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
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specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
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specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c'))
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@ -24,10 +24,10 @@
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#include "qapi/error.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "hw/char/riscv_htif.h"
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#include "hw/char/serial.h"
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#include "hw/char/serial.h"
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#include "chardev/char.h"
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#include "chardev/char.h"
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#include "chardev/char-fe.h"
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#include "chardev/char-fe.h"
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#include "hw/riscv/riscv_htif.h"
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#include "qemu/timer.h"
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#include "qemu/timer.h"
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#include "qemu/error-report.h"
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#include "qemu/error-report.h"
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@ -1,6 +1,3 @@
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config HTIF
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bool
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config HART
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config HART
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bool
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bool
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@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c'))
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@ -31,11 +31,11 @@
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#include "hw/loader.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_htif.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/spike.h"
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#include "hw/riscv/spike.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/boot.h"
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#include "hw/riscv/numa.h"
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#include "hw/riscv/numa.h"
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#include "hw/char/riscv_htif.h"
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#include "hw/intc/sifive_clint.h"
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#include "hw/intc/sifive_clint.h"
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#include "chardev/char.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/arch_init.h"
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