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target/microblaze: Split out FSR from env->sregs

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Continue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 21:54:38 -07:00
parent 78e9caf2f9
commit 5a8e01366c
5 changed files with 13 additions and 10 deletions
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4
linux-user/microblaze/cpu_loop.c
View File

@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env)
case ESR_EC_FPU:
info.si_signo = TARGET_SIGFPE;
info.si_errno = 0;
if (env->sregs[SR_FSR] & FSR_IO) {
if (env->fsr & FSR_IO) {
info.si_code = TARGET_FPE_FLTINV;
}
if (env->sregs[SR_FSR] & FSR_DZ) {
if (env->fsr & FSR_DZ) {
info.si_code = TARGET_FPE_FLTDIV;
}
info._sifields._sigfault._addr = 0;

1
target/microblaze/cpu.h
View File

@ -240,6 +240,7 @@ struct CPUMBState {
uint64_t msr;
uint64_t ear;
uint64_t esr;
uint64_t fsr;
uint64_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */

4
target/microblaze/gdbstub.c
View File

@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
val = env->esr;
break;
case GDB_FSR:
val = env->sregs[SR_FSR];
val = env->fsr;
break;
case GDB_BTR:
val = env->sregs[SR_BTR];
@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->esr = tmp;
break;
case GDB_FSR:
env->sregs[SR_FSR] = tmp;
env->fsr = tmp;
break;
case GDB_BTR:
env->sregs[SR_BTR] = tmp;

8
target/microblaze/op_helper.c
View File

@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int flags)
int raise = 0;
if (flags & float_flag_invalid) {
env->sregs[SR_FSR] |= FSR_IO;
env->fsr |= FSR_IO;
raise = 1;
}
if (flags & float_flag_divbyzero) {
env->sregs[SR_FSR] |= FSR_DZ;
env->fsr |= FSR_DZ;
raise = 1;
}
if (flags & float_flag_overflow) {
env->sregs[SR_FSR] |= FSR_OF;
env->fsr |= FSR_OF;
raise = 1;
}
if (flags & float_flag_underflow) {
env->sregs[SR_FSR] |= FSR_UF;
env->fsr |= FSR_UF;
raise = 1;
}
if (raise

6
target/microblaze/translate.c
View File

@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
env->debug, env->imm, env->iflags, env->fsr,
env->sregs[SR_BTR]);
qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
"eip=%d ie=%d\n",
@ -1877,8 +1877,10 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_SR[SR_ESR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
cpu_SR[SR_FSR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);