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target/microblaze: Split out ESR from env->sregs

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Continue eliminating the sregs array in favor of individual members.
Does not correct the width of ESR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 21:50:35 -07:00
parent b2e80a3c19
commit 78e9caf2f9
6 changed files with 27 additions and 25 deletions
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6
linux-user/microblaze/cpu_loop.c
View File

@ -78,14 +78,14 @@ void cpu_loop(CPUMBState *env)
case EXCP_HW_EXCP:
env->regs[17] = env->pc + 4;
if (env->iflags & D_FLAG) {
env->sregs[SR_ESR] |= 1 << 12;
env->esr |= 1 << 12;
env->pc -= 4;
/* FIXME: if branch was immed, replay the imm as well. */
}
env->iflags &= ~(IMM_FLAG | D_FLAG);
switch (env->sregs[SR_ESR] & 31) {
switch (env->esr & 31) {
case ESR_EC_DIVZERO:
info.si_signo = TARGET_SIGFPE;
info.si_errno = 0;
@ -107,7 +107,7 @@ void cpu_loop(CPUMBState *env)
break;
default:
fprintf(stderr, "Unhandled hw-exception: 0x%" PRIx64 "\n",
env->sregs[SR_ESR] & ESR_EC_MASK);
env->esr & ESR_EC_MASK);
cpu_dump_state(cs, stderr, 0);
exit(EXIT_FAILURE);
break;

1
target/microblaze/cpu.h
View File

@ -239,6 +239,7 @@ struct CPUMBState {
uint64_t pc;
uint64_t msr;
uint64_t ear;
uint64_t esr;
uint64_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */

4
target/microblaze/gdbstub.c
View File

@ -68,7 +68,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
val = env->ear;
break;
case GDB_ESR:
val = env->sregs[SR_ESR];
val = env->esr;
break;
case GDB_FSR:
val = env->sregs[SR_FSR];
@ -124,7 +124,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->ear = tmp;
break;
case GDB_ESR:
env->sregs[SR_ESR] = tmp;
env->esr = tmp;
break;
case GDB_FSR:
env->sregs[SR_FSR] = tmp;

18
target/microblaze/helper.c
View File

@ -88,12 +88,12 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
env->ear = address;
switch (lu.err) {
case ERR_PROT:
env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 17 : 16;
env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10;
env->esr = access_type == MMU_INST_FETCH ? 17 : 16;
env->esr |= (access_type == MMU_DATA_STORE) << 10;
break;
case ERR_MISS:
env->sregs[SR_ESR] = access_type == MMU_INST_FETCH ? 19 : 18;
env->sregs[SR_ESR] |= (access_type == MMU_DATA_STORE) << 10;
env->esr = access_type == MMU_INST_FETCH ? 19 : 18;
env->esr |= (access_type == MMU_DATA_STORE) << 10;
break;
default:
abort();
@ -127,11 +127,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
}
env->regs[17] = env->pc + 4;
env->sregs[SR_ESR] &= ~(1 << 12);
env->esr &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
if (env->iflags & D_FLAG) {
env->sregs[SR_ESR] |= 1 << 12 ;
env->esr |= 1 << 12 ;
env->sregs[SR_BTR] = env->btarget;
}
@ -146,7 +146,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
"esr=%" PRIx64 " iflags=%x\n",
env->pc, env->ear,
env->sregs[SR_ESR], env->iflags);
env->esr, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->pc = cpu->cfg.base_vectors + 0x20;
@ -155,11 +155,11 @@ void mb_cpu_do_interrupt(CPUState *cs)
case EXCP_MMU:
env->regs[17] = env->pc;
env->sregs[SR_ESR] &= ~(1 << 12);
env->esr &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
if (env->iflags & D_FLAG) {
D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
env->sregs[SR_ESR] |= 1 << 12 ;
env->esr |= 1 << 12 ;
env->sregs[SR_BTR] = env->btarget;
/* Reexecute the branch. */

17
target/microblaze/op_helper.c
View File

@ -78,7 +78,7 @@ void helper_debug(CPUMBState *env)
qemu_log("PC=%" PRIx64 "\n", env->pc);
qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
env->msr, env->sregs[SR_ESR], env->ear,
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags);
qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
env->btaken, env->btarget,
@ -138,7 +138,7 @@ static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
env->msr |= MSR_DZ;
if ((env->msr & MSR_EE) && cpu->cfg.div_zero_exception) {
env->sregs[SR_ESR] = ESR_EC_DIVZERO;
env->esr = ESR_EC_DIVZERO;
helper_raise_exception(env, EXCP_HW_EXCP);
}
return 0;
@ -166,7 +166,7 @@ uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
/* raise FPU exception. */
static void raise_fpu_exception(CPUMBState *env)
{
env->sregs[SR_ESR] = ESR_EC_FPU;
env->esr = ESR_EC_FPU;
helper_raise_exception(env, EXCP_HW_EXCP);
}
@ -432,10 +432,9 @@ void helper_memalign(CPUMBState *env, target_ulong addr,
" mask=%x, wr=%d dr=r%d\n",
addr, mask, wr, dr);
env->ear = addr;
env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
| (dr & 31) << 5;
env->esr = ESR_EC_UNALIGNED_DATA | (wr << 10) | (dr & 31) << 5;
if (mask == 3) {
env->sregs[SR_ESR] |= 1 << 11;
env->esr |= 1 << 11;
}
if (!(env->msr & MSR_EE)) {
return;
@ -451,7 +450,7 @@ void helper_stackprot(CPUMBState *env, target_ulong addr)
TARGET_FMT_lx " %x %x\n",
addr, env->slr, env->shr);
env->ear = addr;
env->sregs[SR_ESR] = ESR_EC_STACKPROT;
env->esr = ESR_EC_STACKPROT;
helper_raise_exception(env, EXCP_HW_EXCP);
}
}
@ -491,12 +490,12 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
env->ear = addr;
if (access_type == MMU_INST_FETCH) {
if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
env->esr = ESR_EC_INSN_BUS;
helper_raise_exception(env, EXCP_HW_EXCP);
}
} else {
if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
env->esr = ESR_EC_DATA_BUS;
helper_raise_exception(env, EXCP_HW_EXCP);
}
}

6
target/microblaze/translate.c
View File

@ -1809,7 +1809,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
env->msr, env->sregs[SR_ESR], env->ear,
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags, env->sregs[SR_FSR],
env->sregs[SR_BTR]);
qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
@ -1875,8 +1875,10 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
cpu_SR[SR_EAR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
cpu_SR[SR_ESR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
for (i = SR_EAR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
for (i = SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);