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Add LASX instructions support.

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Merge tag 'pull-loongarch-20230920' of https://gitlab.com/gaosong/qemu into staging

Add LASX instructions support.

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# gpg:                using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
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* tag 'pull-loongarch-20230920' of https://gitlab.com/gaosong/qemu: (57 commits)
  target/loongarch: CPUCFG support LASX
  target/loongarch: Move simply DO_XX marcos togther
  target/loongarch: Implement xvld xvst
  target/loongarch: Implement xvshuf xvperm{i} xvshuf4i
  target/loongarch: Implement xvpack xvpick xvilv{l/h}
  target/loongarch: Implement xvreplve xvinsve0 xvpickve
  target/loongarch: Implement xvinsgr2vr xvpickve2gr
  target/loongarch: Implement xvbitsel xvset
  target/loongarch: Implement xvfcmp
  target/loongarch: Implement xvseq xvsle xvslt
  target/loongarch: Implement LASX fpu fcvt instructions
  target/loongarch: Implement LASX fpu arith instructions
  target/loongarch: Implement xvfrstp
  target/loongarch: Implement xvbitclr xvbitset xvbitrev
  target/loongarch: Implement xvpcnt
  target/loongarch: Implement xvclo xvclz
  target/loongarch: Implement xvssrlrn xvssrarn
  target/loongarch: Implement xvssrln xvssran
  target/loongarch: Implement xvsrlrn xvsrarn
  target/loongarch: Implement xvsrln xvsran
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-09-20 13:56:18 -04:00
commit 55394dcbec
16 changed files with 7350 additions and 4051 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
linux-user/loongarch64/signal.c
View File

@ -12,6 +12,7 @@
#include "linux-user/trace.h"
#include "target/loongarch/internals.h"
#include "target/loongarch/vec.h"
/* FP context was used */
#define SC_USED_FP (1 << 0)

4
target/loongarch/cpu.c
View File

@ -19,6 +19,7 @@
#include "cpu-csr.h"
#include "sysemu/reset.h"
#include "tcg/tcg.h"
#include "vec.h"
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@ -54,6 +55,7 @@ static const char * const excp_names[] = {
[EXCCODE_DBP] = "Debug breakpoint",
[EXCCODE_BCE] = "Bound Check Exception",
[EXCCODE_SXD] = "128 bit vector instructions Disable exception",
[EXCCODE_ASXD] = "256 bit vector instructions Disable exception",
};
const char *loongarch_exception_name(int32_t exception)
@ -189,6 +191,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
case EXCCODE_FPD:
case EXCCODE_FPE:
case EXCCODE_SXD:
case EXCCODE_ASXD:
env->CSR_BADV = env->pc;
QEMU_FALLTHROUGH;
case EXCCODE_BCE:
@ -390,6 +393,7 @@ static void loongarch_la464_initfn(Object *obj)
data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
data = FIELD_DP32(data, CPUCFG2, LSX, 1),
data = FIELD_DP32(data, CPUCFG2, LASX, 1),
data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
data = FIELD_DP32(data, CPUCFG2, LSPW, 1);

26
target/loongarch/cpu.h
View File

@ -251,18 +251,20 @@ FIELD(TLB_MISC, ASID, 1, 10)
FIELD(TLB_MISC, VPPN, 13, 35)
FIELD(TLB_MISC, PS, 48, 6)
#define LSX_LEN (128)
#define LSX_LEN (128)
#define LASX_LEN (256)
typedef union VReg {
int8_t B[LSX_LEN / 8];
int16_t H[LSX_LEN / 16];
int32_t W[LSX_LEN / 32];
int64_t D[LSX_LEN / 64];
uint8_t UB[LSX_LEN / 8];
uint16_t UH[LSX_LEN / 16];
uint32_t UW[LSX_LEN / 32];
uint64_t UD[LSX_LEN / 64];
Int128 Q[LSX_LEN / 128];
}VReg;
int8_t B[LASX_LEN / 8];
int16_t H[LASX_LEN / 16];
int32_t W[LASX_LEN / 32];
int64_t D[LASX_LEN / 64];
uint8_t UB[LASX_LEN / 8];
uint16_t UH[LASX_LEN / 16];
uint32_t UW[LASX_LEN / 32];
uint64_t UD[LASX_LEN / 64];
Int128 Q[LASX_LEN / 128];
} VReg;
typedef union fpr_t fpr_t;
union fpr_t {
@ -460,6 +462,7 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
#define HW_FLAGS_EUEN_ASXE 0x10
#define HW_FLAGS_VA32 0x20
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
@ -470,6 +473,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE;
*flags |= is_va32(env) * HW_FLAGS_VA32;
}

924
target/loongarch/disas.c
View File

@ -1695,3 +1695,927 @@ INSN_LSX(vstelm_d, vr_ii)
INSN_LSX(vstelm_w, vr_ii)
INSN_LSX(vstelm_h, vr_ii)
INSN_LSX(vstelm_b, vr_ii)
#define INSN_LASX(insn, type) \
static bool trans_##insn(DisasContext *ctx, arg_##type * a) \
{ \
output_##type ## _x(ctx, a, #insn); \
return true; \
}
static void output_cv_x(DisasContext *ctx, arg_cv *a, const char *mnemonic)
{
output(ctx, mnemonic, "fcc%d, x%d", a->cd, a->vj);
}
static void output_v_i_x(DisasContext *ctx, arg_v_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, 0x%x", a->vd, a->imm);
}
static void output_vvvv_x(DisasContext *ctx, arg_vvvv *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d, x%d", a->vd, a->vj, a->vk, a->va);
}
static void output_vvv_x(DisasContext *ctx, arg_vvv * a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
}
static void output_vr_x(DisasContext *ctx, arg_vr *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d", a->vd, a->rj);
}
static void output_vv_i_x(DisasContext *ctx, arg_vv_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, 0x%x", a->vd, a->vj, a->imm);
}
static void output_vv_x(DisasContext *ctx, arg_vv *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d", a->vd, a->vj);
}
static void output_vr_i_x(DisasContext *ctx, arg_vr_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d, 0x%x", a->vd, a->rj, a->imm);
}
static void output_rv_i_x(DisasContext *ctx, arg_rv_i *a, const char *mnemonic)
{
output(ctx, mnemonic, "r%d, x%d, 0x%x", a->rd, a->vj, a->imm);
}
static void output_vvr_x(DisasContext *ctx, arg_vvr *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, x%d, r%d", a->vd, a->vj, a->rk);
}
static void output_vrr_x(DisasContext *ctx, arg_vrr *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d, r%d", a->vd, a->rj, a->rk);
}
static void output_vr_ii_x(DisasContext *ctx, arg_vr_ii *a, const char *mnemonic)
{
output(ctx, mnemonic, "x%d, r%d, 0x%x, 0x%x", a->vd, a->rj, a->imm, a->imm2);
}
INSN_LASX(xvadd_b, vvv)
INSN_LASX(xvadd_h, vvv)
INSN_LASX(xvadd_w, vvv)
INSN_LASX(xvadd_d, vvv)
INSN_LASX(xvadd_q, vvv)
INSN_LASX(xvsub_b, vvv)
INSN_LASX(xvsub_h, vvv)
INSN_LASX(xvsub_w, vvv)
INSN_LASX(xvsub_d, vvv)
INSN_LASX(xvsub_q, vvv)
INSN_LASX(xvaddi_bu, vv_i)
INSN_LASX(xvaddi_hu, vv_i)
INSN_LASX(xvaddi_wu, vv_i)
INSN_LASX(xvaddi_du, vv_i)
INSN_LASX(xvsubi_bu, vv_i)
INSN_LASX(xvsubi_hu, vv_i)
INSN_LASX(xvsubi_wu, vv_i)
INSN_LASX(xvsubi_du, vv_i)
INSN_LASX(xvneg_b, vv)
INSN_LASX(xvneg_h, vv)
INSN_LASX(xvneg_w, vv)
INSN_LASX(xvneg_d, vv)
INSN_LASX(xvsadd_b, vvv)
INSN_LASX(xvsadd_h, vvv)
INSN_LASX(xvsadd_w, vvv)
INSN_LASX(xvsadd_d, vvv)
INSN_LASX(xvsadd_bu, vvv)
INSN_LASX(xvsadd_hu, vvv)
INSN_LASX(xvsadd_wu, vvv)
INSN_LASX(xvsadd_du, vvv)
INSN_LASX(xvssub_b, vvv)
INSN_LASX(xvssub_h, vvv)
INSN_LASX(xvssub_w, vvv)
INSN_LASX(xvssub_d, vvv)
INSN_LASX(xvssub_bu, vvv)
INSN_LASX(xvssub_hu, vvv)
INSN_LASX(xvssub_wu, vvv)
INSN_LASX(xvssub_du, vvv)
INSN_LASX(xvhaddw_h_b, vvv)
INSN_LASX(xvhaddw_w_h, vvv)
INSN_LASX(xvhaddw_d_w, vvv)
INSN_LASX(xvhaddw_q_d, vvv)
INSN_LASX(xvhaddw_hu_bu, vvv)
INSN_LASX(xvhaddw_wu_hu, vvv)
INSN_LASX(xvhaddw_du_wu, vvv)
INSN_LASX(xvhaddw_qu_du, vvv)
INSN_LASX(xvhsubw_h_b, vvv)
INSN_LASX(xvhsubw_w_h, vvv)
INSN_LASX(xvhsubw_d_w, vvv)
INSN_LASX(xvhsubw_q_d, vvv)
INSN_LASX(xvhsubw_hu_bu, vvv)
INSN_LASX(xvhsubw_wu_hu, vvv)
INSN_LASX(xvhsubw_du_wu, vvv)
INSN_LASX(xvhsubw_qu_du, vvv)
INSN_LASX(xvaddwev_h_b, vvv)
INSN_LASX(xvaddwev_w_h, vvv)
INSN_LASX(xvaddwev_d_w, vvv)
INSN_LASX(xvaddwev_q_d, vvv)
INSN_LASX(xvaddwod_h_b, vvv)
INSN_LASX(xvaddwod_w_h, vvv)
INSN_LASX(xvaddwod_d_w, vvv)
INSN_LASX(xvaddwod_q_d, vvv)
INSN_LASX(xvsubwev_h_b, vvv)
INSN_LASX(xvsubwev_w_h, vvv)
INSN_LASX(xvsubwev_d_w, vvv)
INSN_LASX(xvsubwev_q_d, vvv)
INSN_LASX(xvsubwod_h_b, vvv)
INSN_LASX(xvsubwod_w_h, vvv)
INSN_LASX(xvsubwod_d_w, vvv)
INSN_LASX(xvsubwod_q_d, vvv)
INSN_LASX(xvaddwev_h_bu, vvv)
INSN_LASX(xvaddwev_w_hu, vvv)
INSN_LASX(xvaddwev_d_wu, vvv)
INSN_LASX(xvaddwev_q_du, vvv)
INSN_LASX(xvaddwod_h_bu, vvv)
INSN_LASX(xvaddwod_w_hu, vvv)
INSN_LASX(xvaddwod_d_wu, vvv)
INSN_LASX(xvaddwod_q_du, vvv)
INSN_LASX(xvsubwev_h_bu, vvv)
INSN_LASX(xvsubwev_w_hu, vvv)
INSN_LASX(xvsubwev_d_wu, vvv)
INSN_LASX(xvsubwev_q_du, vvv)
INSN_LASX(xvsubwod_h_bu, vvv)
INSN_LASX(xvsubwod_w_hu, vvv)
INSN_LASX(xvsubwod_d_wu, vvv)
INSN_LASX(xvsubwod_q_du, vvv)
INSN_LASX(xvaddwev_h_bu_b, vvv)
INSN_LASX(xvaddwev_w_hu_h, vvv)
INSN_LASX(xvaddwev_d_wu_w, vvv)
INSN_LASX(xvaddwev_q_du_d, vvv)
INSN_LASX(xvaddwod_h_bu_b, vvv)
INSN_LASX(xvaddwod_w_hu_h, vvv)
INSN_LASX(xvaddwod_d_wu_w, vvv)
INSN_LASX(xvaddwod_q_du_d, vvv)
INSN_LASX(xvavg_b, vvv)
INSN_LASX(xvavg_h, vvv)
INSN_LASX(xvavg_w, vvv)
INSN_LASX(xvavg_d, vvv)
INSN_LASX(xvavg_bu, vvv)
INSN_LASX(xvavg_hu, vvv)
INSN_LASX(xvavg_wu, vvv)
INSN_LASX(xvavg_du, vvv)
INSN_LASX(xvavgr_b, vvv)
INSN_LASX(xvavgr_h, vvv)
INSN_LASX(xvavgr_w, vvv)
INSN_LASX(xvavgr_d, vvv)
INSN_LASX(xvavgr_bu, vvv)
INSN_LASX(xvavgr_hu, vvv)
INSN_LASX(xvavgr_wu, vvv)
INSN_LASX(xvavgr_du, vvv)
INSN_LASX(xvabsd_b, vvv)
INSN_LASX(xvabsd_h, vvv)
INSN_LASX(xvabsd_w, vvv)
INSN_LASX(xvabsd_d, vvv)
INSN_LASX(xvabsd_bu, vvv)
INSN_LASX(xvabsd_hu, vvv)
INSN_LASX(xvabsd_wu, vvv)
INSN_LASX(xvabsd_du, vvv)
INSN_LASX(xvadda_b, vvv)
INSN_LASX(xvadda_h, vvv)
INSN_LASX(xvadda_w, vvv)
INSN_LASX(xvadda_d, vvv)
INSN_LASX(xvmax_b, vvv)
INSN_LASX(xvmax_h, vvv)
INSN_LASX(xvmax_w, vvv)
INSN_LASX(xvmax_d, vvv)
INSN_LASX(xvmin_b, vvv)
INSN_LASX(xvmin_h, vvv)
INSN_LASX(xvmin_w, vvv)
INSN_LASX(xvmin_d, vvv)
INSN_LASX(xvmax_bu, vvv)
INSN_LASX(xvmax_hu, vvv)
INSN_LASX(xvmax_wu, vvv)
INSN_LASX(xvmax_du, vvv)
INSN_LASX(xvmin_bu, vvv)
INSN_LASX(xvmin_hu, vvv)
INSN_LASX(xvmin_wu, vvv)
INSN_LASX(xvmin_du, vvv)
INSN_LASX(xvmaxi_b, vv_i)
INSN_LASX(xvmaxi_h, vv_i)
INSN_LASX(xvmaxi_w, vv_i)
INSN_LASX(xvmaxi_d, vv_i)
INSN_LASX(xvmini_b, vv_i)
INSN_LASX(xvmini_h, vv_i)
INSN_LASX(xvmini_w, vv_i)
INSN_LASX(xvmini_d, vv_i)
INSN_LASX(xvmaxi_bu, vv_i)
INSN_LASX(xvmaxi_hu, vv_i)
INSN_LASX(xvmaxi_wu, vv_i)
INSN_LASX(xvmaxi_du, vv_i)
INSN_LASX(xvmini_bu, vv_i)
INSN_LASX(xvmini_hu, vv_i)
INSN_LASX(xvmini_wu, vv_i)
INSN_LASX(xvmini_du, vv_i)
INSN_LASX(xvmul_b, vvv)
INSN_LASX(xvmul_h, vvv)
INSN_LASX(xvmul_w, vvv)
INSN_LASX(xvmul_d, vvv)
INSN_LASX(xvmuh_b, vvv)
INSN_LASX(xvmuh_h, vvv)
INSN_LASX(xvmuh_w, vvv)
INSN_LASX(xvmuh_d, vvv)
INSN_LASX(xvmuh_bu, vvv)
INSN_LASX(xvmuh_hu, vvv)
INSN_LASX(xvmuh_wu, vvv)
INSN_LASX(xvmuh_du, vvv)
INSN_LASX(xvmulwev_h_b, vvv)
INSN_LASX(xvmulwev_w_h, vvv)
INSN_LASX(xvmulwev_d_w, vvv)
INSN_LASX(xvmulwev_q_d, vvv)
INSN_LASX(xvmulwod_h_b, vvv)
INSN_LASX(xvmulwod_w_h, vvv)
INSN_LASX(xvmulwod_d_w, vvv)
INSN_LASX(xvmulwod_q_d, vvv)
INSN_LASX(xvmulwev_h_bu, vvv)
INSN_LASX(xvmulwev_w_hu, vvv)
INSN_LASX(xvmulwev_d_wu, vvv)
INSN_LASX(xvmulwev_q_du, vvv)
INSN_LASX(xvmulwod_h_bu, vvv)
INSN_LASX(xvmulwod_w_hu, vvv)
INSN_LASX(xvmulwod_d_wu, vvv)
INSN_LASX(xvmulwod_q_du, vvv)
INSN_LASX(xvmulwev_h_bu_b, vvv)
INSN_LASX(xvmulwev_w_hu_h, vvv)
INSN_LASX(xvmulwev_d_wu_w, vvv)
INSN_LASX(xvmulwev_q_du_d, vvv)
INSN_LASX(xvmulwod_h_bu_b, vvv)
INSN_LASX(xvmulwod_w_hu_h, vvv)
INSN_LASX(xvmulwod_d_wu_w, vvv)
INSN_LASX(xvmulwod_q_du_d, vvv)
INSN_LASX(xvmadd_b, vvv)
INSN_LASX(xvmadd_h, vvv)
INSN_LASX(xvmadd_w, vvv)
INSN_LASX(xvmadd_d, vvv)
INSN_LASX(xvmsub_b, vvv)
INSN_LASX(xvmsub_h, vvv)
INSN_LASX(xvmsub_w, vvv)
INSN_LASX(xvmsub_d, vvv)
INSN_LASX(xvmaddwev_h_b, vvv)
INSN_LASX(xvmaddwev_w_h, vvv)
INSN_LASX(xvmaddwev_d_w, vvv)
INSN_LASX(xvmaddwev_q_d, vvv)
INSN_LASX(xvmaddwod_h_b, vvv)
INSN_LASX(xvmaddwod_w_h, vvv)
INSN_LASX(xvmaddwod_d_w, vvv)
INSN_LASX(xvmaddwod_q_d, vvv)
INSN_LASX(xvmaddwev_h_bu, vvv)
INSN_LASX(xvmaddwev_w_hu, vvv)
INSN_LASX(xvmaddwev_d_wu, vvv)
INSN_LASX(xvmaddwev_q_du, vvv)
INSN_LASX(xvmaddwod_h_bu, vvv)
INSN_LASX(xvmaddwod_w_hu, vvv)
INSN_LASX(xvmaddwod_d_wu, vvv)
INSN_LASX(xvmaddwod_q_du, vvv)
INSN_LASX(xvmaddwev_h_bu_b, vvv)
INSN_LASX(xvmaddwev_w_hu_h, vvv)
INSN_LASX(xvmaddwev_d_wu_w, vvv)
INSN_LASX(xvmaddwev_q_du_d, vvv)
INSN_LASX(xvmaddwod_h_bu_b, vvv)
INSN_LASX(xvmaddwod_w_hu_h, vvv)
INSN_LASX(xvmaddwod_d_wu_w, vvv)
INSN_LASX(xvmaddwod_q_du_d, vvv)
INSN_LASX(xvdiv_b, vvv)
INSN_LASX(xvdiv_h, vvv)
INSN_LASX(xvdiv_w, vvv)
INSN_LASX(xvdiv_d, vvv)
INSN_LASX(xvdiv_bu, vvv)
INSN_LASX(xvdiv_hu, vvv)
INSN_LASX(xvdiv_wu, vvv)
INSN_LASX(xvdiv_du, vvv)
INSN_LASX(xvmod_b, vvv)
INSN_LASX(xvmod_h, vvv)
INSN_LASX(xvmod_w, vvv)
INSN_LASX(xvmod_d, vvv)
INSN_LASX(xvmod_bu, vvv)
INSN_LASX(xvmod_hu, vvv)
INSN_LASX(xvmod_wu, vvv)
INSN_LASX(xvmod_du, vvv)
INSN_LASX(xvsat_b, vv_i)
INSN_LASX(xvsat_h, vv_i)
INSN_LASX(xvsat_w, vv_i)
INSN_LASX(xvsat_d, vv_i)
INSN_LASX(xvsat_bu, vv_i)
INSN_LASX(xvsat_hu, vv_i)
INSN_LASX(xvsat_wu, vv_i)
INSN_LASX(xvsat_du, vv_i)
INSN_LASX(xvexth_h_b, vv)
INSN_LASX(xvexth_w_h, vv)
INSN_LASX(xvexth_d_w, vv)
INSN_LASX(xvexth_q_d, vv)
INSN_LASX(xvexth_hu_bu, vv)
INSN_LASX(xvexth_wu_hu, vv)
INSN_LASX(xvexth_du_wu, vv)
INSN_LASX(xvexth_qu_du, vv)
INSN_LASX(vext2xv_h_b, vv)
INSN_LASX(vext2xv_w_b, vv)
INSN_LASX(vext2xv_d_b, vv)
INSN_LASX(vext2xv_w_h, vv)
INSN_LASX(vext2xv_d_h, vv)
INSN_LASX(vext2xv_d_w, vv)
INSN_LASX(vext2xv_hu_bu, vv)
INSN_LASX(vext2xv_wu_bu, vv)
INSN_LASX(vext2xv_du_bu, vv)
INSN_LASX(vext2xv_wu_hu, vv)
INSN_LASX(vext2xv_du_hu, vv)
INSN_LASX(vext2xv_du_wu, vv)
INSN_LASX(xvsigncov_b, vvv)
INSN_LASX(xvsigncov_h, vvv)
INSN_LASX(xvsigncov_w, vvv)
INSN_LASX(xvsigncov_d, vvv)
INSN_LASX(xvmskltz_b, vv)
INSN_LASX(xvmskltz_h, vv)
INSN_LASX(xvmskltz_w, vv)
INSN_LASX(xvmskltz_d, vv)
INSN_LASX(xvmskgez_b, vv)
INSN_LASX(xvmsknz_b, vv)
INSN_LASX(xvldi, v_i)
INSN_LASX(xvand_v, vvv)
INSN_LASX(xvor_v, vvv)
INSN_LASX(xvxor_v, vvv)
INSN_LASX(xvnor_v, vvv)
INSN_LASX(xvandn_v, vvv)
INSN_LASX(xvorn_v, vvv)
INSN_LASX(xvandi_b, vv_i)
INSN_LASX(xvori_b, vv_i)
INSN_LASX(xvxori_b, vv_i)
INSN_LASX(xvnori_b, vv_i)
INSN_LASX(xvsll_b, vvv)
INSN_LASX(xvsll_h, vvv)
INSN_LASX(xvsll_w, vvv)
INSN_LASX(xvsll_d, vvv)
INSN_LASX(xvslli_b, vv_i)
INSN_LASX(xvslli_h, vv_i)
INSN_LASX(xvslli_w, vv_i)
INSN_LASX(xvslli_d, vv_i)
INSN_LASX(xvsrl_b, vvv)
INSN_LASX(xvsrl_h, vvv)
INSN_LASX(xvsrl_w, vvv)
INSN_LASX(xvsrl_d, vvv)
INSN_LASX(xvsrli_b, vv_i)
INSN_LASX(xvsrli_h, vv_i)
INSN_LASX(xvsrli_w, vv_i)
INSN_LASX(xvsrli_d, vv_i)
INSN_LASX(xvsra_b, vvv)
INSN_LASX(xvsra_h, vvv)
INSN_LASX(xvsra_w, vvv)
INSN_LASX(xvsra_d, vvv)
INSN_LASX(xvsrai_b, vv_i)
INSN_LASX(xvsrai_h, vv_i)
INSN_LASX(xvsrai_w, vv_i)
INSN_LASX(xvsrai_d, vv_i)
INSN_LASX(xvrotr_b, vvv)
INSN_LASX(xvrotr_h, vvv)
INSN_LASX(xvrotr_w, vvv)
INSN_LASX(xvrotr_d, vvv)
INSN_LASX(xvrotri_b, vv_i)
INSN_LASX(xvrotri_h, vv_i)
INSN_LASX(xvrotri_w, vv_i)
INSN_LASX(xvrotri_d, vv_i)
INSN_LASX(xvsllwil_h_b, vv_i)
INSN_LASX(xvsllwil_w_h, vv_i)
INSN_LASX(xvsllwil_d_w, vv_i)
INSN_LASX(xvextl_q_d, vv)
INSN_LASX(xvsllwil_hu_bu, vv_i)
INSN_LASX(xvsllwil_wu_hu, vv_i)
INSN_LASX(xvsllwil_du_wu, vv_i)
INSN_LASX(xvextl_qu_du, vv)
INSN_LASX(xvsrlr_b, vvv)
INSN_LASX(xvsrlr_h, vvv)
INSN_LASX(xvsrlr_w, vvv)
INSN_LASX(xvsrlr_d, vvv)
INSN_LASX(xvsrlri_b, vv_i)
INSN_LASX(xvsrlri_h, vv_i)
INSN_LASX(xvsrlri_w, vv_i)
INSN_LASX(xvsrlri_d, vv_i)
INSN_LASX(xvsrar_b, vvv)
INSN_LASX(xvsrar_h, vvv)
INSN_LASX(xvsrar_w, vvv)
INSN_LASX(xvsrar_d, vvv)
INSN_LASX(xvsrari_b, vv_i)
INSN_LASX(xvsrari_h, vv_i)
INSN_LASX(xvsrari_w, vv_i)
INSN_LASX(xvsrari_d, vv_i)
INSN_LASX(xvsrln_b_h, vvv)
INSN_LASX(xvsrln_h_w, vvv)
INSN_LASX(xvsrln_w_d, vvv)
INSN_LASX(xvsran_b_h, vvv)
INSN_LASX(xvsran_h_w, vvv)
INSN_LASX(xvsran_w_d, vvv)
INSN_LASX(xvsrlni_b_h, vv_i)
INSN_LASX(xvsrlni_h_w, vv_i)
INSN_LASX(xvsrlni_w_d, vv_i)
INSN_LASX(xvsrlni_d_q, vv_i)
INSN_LASX(xvsrani_b_h, vv_i)
INSN_LASX(xvsrani_h_w, vv_i)
INSN_LASX(xvsrani_w_d, vv_i)
INSN_LASX(xvsrani_d_q, vv_i)
INSN_LASX(xvsrlrn_b_h, vvv)
INSN_LASX(xvsrlrn_h_w, vvv)
INSN_LASX(xvsrlrn_w_d, vvv)
INSN_LASX(xvsrarn_b_h, vvv)
INSN_LASX(xvsrarn_h_w, vvv)
INSN_LASX(xvsrarn_w_d, vvv)
INSN_LASX(xvsrlrni_b_h, vv_i)
INSN_LASX(xvsrlrni_h_w, vv_i)
INSN_LASX(xvsrlrni_w_d, vv_i)
INSN_LASX(xvsrlrni_d_q, vv_i)
INSN_LASX(xvsrarni_b_h, vv_i)
INSN_LASX(xvsrarni_h_w, vv_i)
INSN_LASX(xvsrarni_w_d, vv_i)
INSN_LASX(xvsrarni_d_q, vv_i)
INSN_LASX(xvssrln_b_h, vvv)
INSN_LASX(xvssrln_h_w, vvv)
INSN_LASX(xvssrln_w_d, vvv)
INSN_LASX(xvssran_b_h, vvv)
INSN_LASX(xvssran_h_w, vvv)
INSN_LASX(xvssran_w_d, vvv)
INSN_LASX(xvssrln_bu_h, vvv)
INSN_LASX(xvssrln_hu_w, vvv)
INSN_LASX(xvssrln_wu_d, vvv)
INSN_LASX(xvssran_bu_h, vvv)
INSN_LASX(xvssran_hu_w, vvv)
INSN_LASX(xvssran_wu_d, vvv)
INSN_LASX(xvssrlni_b_h, vv_i)
INSN_LASX(xvssrlni_h_w, vv_i)
INSN_LASX(xvssrlni_w_d, vv_i)
INSN_LASX(xvssrlni_d_q, vv_i)
INSN_LASX(xvssrani_b_h, vv_i)
INSN_LASX(xvssrani_h_w, vv_i)
INSN_LASX(xvssrani_w_d, vv_i)
INSN_LASX(xvssrani_d_q, vv_i)
INSN_LASX(xvssrlni_bu_h, vv_i)
INSN_LASX(xvssrlni_hu_w, vv_i)
INSN_LASX(xvssrlni_wu_d, vv_i)
INSN_LASX(xvssrlni_du_q, vv_i)
INSN_LASX(xvssrani_bu_h, vv_i)
INSN_LASX(xvssrani_hu_w, vv_i)
INSN_LASX(xvssrani_wu_d, vv_i)
INSN_LASX(xvssrani_du_q, vv_i)
INSN_LASX(xvssrlrn_b_h, vvv)
INSN_LASX(xvssrlrn_h_w, vvv)
INSN_LASX(xvssrlrn_w_d, vvv)
INSN_LASX(xvssrarn_b_h, vvv)
INSN_LASX(xvssrarn_h_w, vvv)
INSN_LASX(xvssrarn_w_d, vvv)
INSN_LASX(xvssrlrn_bu_h, vvv)
INSN_LASX(xvssrlrn_hu_w, vvv)
INSN_LASX(xvssrlrn_wu_d, vvv)
INSN_LASX(xvssrarn_bu_h, vvv)
INSN_LASX(xvssrarn_hu_w, vvv)
INSN_LASX(xvssrarn_wu_d, vvv)
INSN_LASX(xvssrlrni_b_h, vv_i)
INSN_LASX(xvssrlrni_h_w, vv_i)
INSN_LASX(xvssrlrni_w_d, vv_i)
INSN_LASX(xvssrlrni_d_q, vv_i)
INSN_LASX(xvssrlrni_bu_h, vv_i)
INSN_LASX(xvssrlrni_hu_w, vv_i)
INSN_LASX(xvssrlrni_wu_d, vv_i)
INSN_LASX(xvssrlrni_du_q, vv_i)
INSN_LASX(xvssrarni_b_h, vv_i)
INSN_LASX(xvssrarni_h_w, vv_i)
INSN_LASX(xvssrarni_w_d, vv_i)
INSN_LASX(xvssrarni_d_q, vv_i)
INSN_LASX(xvssrarni_bu_h, vv_i)
INSN_LASX(xvssrarni_hu_w, vv_i)
INSN_LASX(xvssrarni_wu_d, vv_i)
INSN_LASX(xvssrarni_du_q, vv_i)
INSN_LASX(xvclo_b, vv)
INSN_LASX(xvclo_h, vv)
INSN_LASX(xvclo_w, vv)
INSN_LASX(xvclo_d, vv)
INSN_LASX(xvclz_b, vv)
INSN_LASX(xvclz_h, vv)
INSN_LASX(xvclz_w, vv)
INSN_LASX(xvclz_d, vv)
INSN_LASX(xvpcnt_b, vv)
INSN_LASX(xvpcnt_h, vv)
INSN_LASX(xvpcnt_w, vv)
INSN_LASX(xvpcnt_d, vv)
INSN_LASX(xvbitclr_b, vvv)
INSN_LASX(xvbitclr_h, vvv)
INSN_LASX(xvbitclr_w, vvv)
INSN_LASX(xvbitclr_d, vvv)
INSN_LASX(xvbitclri_b, vv_i)
INSN_LASX(xvbitclri_h, vv_i)
INSN_LASX(xvbitclri_w, vv_i)
INSN_LASX(xvbitclri_d, vv_i)
INSN_LASX(xvbitset_b, vvv)
INSN_LASX(xvbitset_h, vvv)
INSN_LASX(xvbitset_w, vvv)
INSN_LASX(xvbitset_d, vvv)
INSN_LASX(xvbitseti_b, vv_i)
INSN_LASX(xvbitseti_h, vv_i)
INSN_LASX(xvbitseti_w, vv_i)
INSN_LASX(xvbitseti_d, vv_i)
INSN_LASX(xvbitrev_b, vvv)
INSN_LASX(xvbitrev_h, vvv)
INSN_LASX(xvbitrev_w, vvv)
INSN_LASX(xvbitrev_d, vvv)
INSN_LASX(xvbitrevi_b, vv_i)
INSN_LASX(xvbitrevi_h, vv_i)
INSN_LASX(xvbitrevi_w, vv_i)
INSN_LASX(xvbitrevi_d, vv_i)
INSN_LASX(xvfrstp_b, vvv)
INSN_LASX(xvfrstp_h, vvv)
INSN_LASX(xvfrstpi_b, vv_i)
INSN_LASX(xvfrstpi_h, vv_i)
INSN_LASX(xvfadd_s, vvv)
INSN_LASX(xvfadd_d, vvv)
INSN_LASX(xvfsub_s, vvv)
INSN_LASX(xvfsub_d, vvv)
INSN_LASX(xvfmul_s, vvv)
INSN_LASX(xvfmul_d, vvv)
INSN_LASX(xvfdiv_s, vvv)
INSN_LASX(xvfdiv_d, vvv)
INSN_LASX(xvfmadd_s, vvvv)
INSN_LASX(xvfmadd_d, vvvv)
INSN_LASX(xvfmsub_s, vvvv)
INSN_LASX(xvfmsub_d, vvvv)
INSN_LASX(xvfnmadd_s, vvvv)
INSN_LASX(xvfnmadd_d, vvvv)
INSN_LASX(xvfnmsub_s, vvvv)
INSN_LASX(xvfnmsub_d, vvvv)
INSN_LASX(xvfmax_s, vvv)
INSN_LASX(xvfmax_d, vvv)
INSN_LASX(xvfmin_s, vvv)
INSN_LASX(xvfmin_d, vvv)
INSN_LASX(xvfmaxa_s, vvv)
INSN_LASX(xvfmaxa_d, vvv)
INSN_LASX(xvfmina_s, vvv)
INSN_LASX(xvfmina_d, vvv)
INSN_LASX(xvflogb_s, vv)
INSN_LASX(xvflogb_d, vv)
INSN_LASX(xvfclass_s, vv)
INSN_LASX(xvfclass_d, vv)
INSN_LASX(xvfsqrt_s, vv)
INSN_LASX(xvfsqrt_d, vv)
INSN_LASX(xvfrecip_s, vv)
INSN_LASX(xvfrecip_d, vv)
INSN_LASX(xvfrsqrt_s, vv)
INSN_LASX(xvfrsqrt_d, vv)
INSN_LASX(xvfcvtl_s_h, vv)
INSN_LASX(xvfcvth_s_h, vv)
INSN_LASX(xvfcvtl_d_s, vv)
INSN_LASX(xvfcvth_d_s, vv)
INSN_LASX(xvfcvt_h_s, vvv)
INSN_LASX(xvfcvt_s_d, vvv)
INSN_LASX(xvfrint_s, vv)
INSN_LASX(xvfrint_d, vv)
INSN_LASX(xvfrintrm_s, vv)
INSN_LASX(xvfrintrm_d, vv)
INSN_LASX(xvfrintrp_s, vv)
INSN_LASX(xvfrintrp_d, vv)
INSN_LASX(xvfrintrz_s, vv)
INSN_LASX(xvfrintrz_d, vv)
INSN_LASX(xvfrintrne_s, vv)
INSN_LASX(xvfrintrne_d, vv)
INSN_LASX(xvftint_w_s, vv)
INSN_LASX(xvftint_l_d, vv)
INSN_LASX(xvftintrm_w_s, vv)
INSN_LASX(xvftintrm_l_d, vv)
INSN_LASX(xvftintrp_w_s, vv)
INSN_LASX(xvftintrp_l_d, vv)
INSN_LASX(xvftintrz_w_s, vv)
INSN_LASX(xvftintrz_l_d, vv)
INSN_LASX(xvftintrne_w_s, vv)
INSN_LASX(xvftintrne_l_d, vv)
INSN_LASX(xvftint_wu_s, vv)
INSN_LASX(xvftint_lu_d, vv)
INSN_LASX(xvftintrz_wu_s, vv)
INSN_LASX(xvftintrz_lu_d, vv)
INSN_LASX(xvftint_w_d, vvv)
INSN_LASX(xvftintrm_w_d, vvv)
INSN_LASX(xvftintrp_w_d, vvv)
INSN_LASX(xvftintrz_w_d, vvv)
INSN_LASX(xvftintrne_w_d, vvv)
INSN_LASX(xvftintl_l_s, vv)
INSN_LASX(xvftinth_l_s, vv)
INSN_LASX(xvftintrml_l_s, vv)
INSN_LASX(xvftintrmh_l_s, vv)
INSN_LASX(xvftintrpl_l_s, vv)
INSN_LASX(xvftintrph_l_s, vv)
INSN_LASX(xvftintrzl_l_s, vv)
INSN_LASX(xvftintrzh_l_s, vv)
INSN_LASX(xvftintrnel_l_s, vv)
INSN_LASX(xvftintrneh_l_s, vv)
INSN_LASX(xvffint_s_w, vv)
INSN_LASX(xvffint_s_wu, vv)
INSN_LASX(xvffint_d_l, vv)
INSN_LASX(xvffint_d_lu, vv)
INSN_LASX(xvffintl_d_w, vv)
INSN_LASX(xvffinth_d_w, vv)
INSN_LASX(xvffint_s_l, vvv)
INSN_LASX(xvseq_b, vvv)
INSN_LASX(xvseq_h, vvv)
INSN_LASX(xvseq_w, vvv)
INSN_LASX(xvseq_d, vvv)
INSN_LASX(xvseqi_b, vv_i)
INSN_LASX(xvseqi_h, vv_i)
INSN_LASX(xvseqi_w, vv_i)
INSN_LASX(xvseqi_d, vv_i)
INSN_LASX(xvsle_b, vvv)
INSN_LASX(xvsle_h, vvv)
INSN_LASX(xvsle_w, vvv)
INSN_LASX(xvsle_d, vvv)
INSN_LASX(xvslei_b, vv_i)
INSN_LASX(xvslei_h, vv_i)
INSN_LASX(xvslei_w, vv_i)
INSN_LASX(xvslei_d, vv_i)
INSN_LASX(xvsle_bu, vvv)
INSN_LASX(xvsle_hu, vvv)
INSN_LASX(xvsle_wu, vvv)
INSN_LASX(xvsle_du, vvv)
INSN_LASX(xvslei_bu, vv_i)
INSN_LASX(xvslei_hu, vv_i)
INSN_LASX(xvslei_wu, vv_i)
INSN_LASX(xvslei_du, vv_i)
INSN_LASX(xvslt_b, vvv)
INSN_LASX(xvslt_h, vvv)
INSN_LASX(xvslt_w, vvv)
INSN_LASX(xvslt_d, vvv)
INSN_LASX(xvslti_b, vv_i)
INSN_LASX(xvslti_h, vv_i)
INSN_LASX(xvslti_w, vv_i)
INSN_LASX(xvslti_d, vv_i)
INSN_LASX(xvslt_bu, vvv)
INSN_LASX(xvslt_hu, vvv)
INSN_LASX(xvslt_wu, vvv)
INSN_LASX(xvslt_du, vvv)
INSN_LASX(xvslti_bu, vv_i)
INSN_LASX(xvslti_hu, vv_i)
INSN_LASX(xvslti_wu, vv_i)
INSN_LASX(xvslti_du, vv_i)
#define output_xvfcmp(C, PREFIX, SUFFIX) \
{ \
(C)->info->fprintf_func((C)->info->stream, "%08x %s%s\tx%d, x%d, x%d", \
(C)->insn, PREFIX, SUFFIX, a->vd, \
a->vj, a->vk); \
}
static bool output_xxx_fcond(DisasContext *ctx, arg_vvv_fcond * a,
const char *suffix)
{
bool ret = true;
switch (a->fcond) {
case 0x0:
output_xvfcmp(ctx, "xvfcmp_caf_", suffix);
break;
case 0x1:
output_xvfcmp(ctx, "xvfcmp_saf_", suffix);
break;
case 0x2:
output_xvfcmp(ctx, "xvfcmp_clt_", suffix);
break;
case 0x3:
output_xvfcmp(ctx, "xvfcmp_slt_", suffix);
break;
case 0x4:
output_xvfcmp(ctx, "xvfcmp_ceq_", suffix);
break;
case 0x5:
output_xvfcmp(ctx, "xvfcmp_seq_", suffix);
break;
case 0x6:
output_xvfcmp(ctx, "xvfcmp_cle_", suffix);
break;
case 0x7:
output_xvfcmp(ctx, "xvfcmp_sle_", suffix);
break;
case 0x8:
output_xvfcmp(ctx, "xvfcmp_cun_", suffix);
break;
case 0x9:
output_xvfcmp(ctx, "xvfcmp_sun_", suffix);
break;
case 0xA:
output_xvfcmp(ctx, "xvfcmp_cult_", suffix);
break;
case 0xB:
output_xvfcmp(ctx, "xvfcmp_sult_", suffix);
break;
case 0xC:
output_xvfcmp(ctx, "xvfcmp_cueq_", suffix);
break;
case 0xD:
output_xvfcmp(ctx, "xvfcmp_sueq_", suffix);
break;
case 0xE:
output_xvfcmp(ctx, "xvfcmp_cule_", suffix);
break;
case 0xF:
output_xvfcmp(ctx, "xvfcmp_sule_", suffix);
break;
case 0x10:
output_xvfcmp(ctx, "xvfcmp_cne_", suffix);
break;
case 0x11:
output_xvfcmp(ctx, "xvfcmp_sne_", suffix);
break;
case 0x14:
output_xvfcmp(ctx, "xvfcmp_cor_", suffix);
break;
case 0x15:
output_xvfcmp(ctx, "xvfcmp_sor_", suffix);
break;
case 0x18:
output_xvfcmp(ctx, "xvfcmp_cune_", suffix);
break;
case 0x19:
output_xvfcmp(ctx, "xvfcmp_sune_", suffix);
break;
default:
ret = false;
}
return ret;
}
#define LASX_FCMP_INSN(suffix) \
static bool trans_xvfcmp_cond_##suffix(DisasContext *ctx, \
arg_vvv_fcond * a) \
{ \
return output_xxx_fcond(ctx, a, #suffix); \
}
LASX_FCMP_INSN(s)
LASX_FCMP_INSN(d)
INSN_LASX(xvbitsel_v, vvvv)
INSN_LASX(xvbitseli_b, vv_i)
INSN_LASX(xvseteqz_v, cv)
INSN_LASX(xvsetnez_v, cv)
INSN_LASX(xvsetanyeqz_b, cv)
INSN_LASX(xvsetanyeqz_h, cv)
INSN_LASX(xvsetanyeqz_w, cv)
INSN_LASX(xvsetanyeqz_d, cv)
INSN_LASX(xvsetallnez_b, cv)
INSN_LASX(xvsetallnez_h, cv)
INSN_LASX(xvsetallnez_w, cv)
INSN_LASX(xvsetallnez_d, cv)
INSN_LASX(xvinsgr2vr_w, vr_i)
INSN_LASX(xvinsgr2vr_d, vr_i)
INSN_LASX(xvpickve2gr_w, rv_i)
INSN_LASX(xvpickve2gr_d, rv_i)
INSN_LASX(xvpickve2gr_wu, rv_i)
INSN_LASX(xvpickve2gr_du, rv_i)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
INSN_LASX(xvreplgr2vr_d, vr)
INSN_LASX(xvreplve_b, vvr)
INSN_LASX(xvreplve_h, vvr)
INSN_LASX(xvreplve_w, vvr)
INSN_LASX(xvreplve_d, vvr)
INSN_LASX(xvrepl128vei_b, vv_i)
INSN_LASX(xvrepl128vei_h, vv_i)
INSN_LASX(xvrepl128vei_w, vv_i)
INSN_LASX(xvrepl128vei_d, vv_i)
INSN_LASX(xvreplve0_b, vv)
INSN_LASX(xvreplve0_h, vv)
INSN_LASX(xvreplve0_w, vv)
INSN_LASX(xvreplve0_d, vv)
INSN_LASX(xvreplve0_q, vv)
INSN_LASX(xvinsve0_w, vv_i)
INSN_LASX(xvinsve0_d, vv_i)
INSN_LASX(xvpickve_w, vv_i)
INSN_LASX(xvpickve_d, vv_i)
INSN_LASX(xvbsll_v, vv_i)
INSN_LASX(xvbsrl_v, vv_i)
INSN_LASX(xvpackev_b, vvv)
INSN_LASX(xvpackev_h, vvv)
INSN_LASX(xvpackev_w, vvv)
INSN_LASX(xvpackev_d, vvv)
INSN_LASX(xvpackod_b, vvv)
INSN_LASX(xvpackod_h, vvv)
INSN_LASX(xvpackod_w, vvv)
INSN_LASX(xvpackod_d, vvv)
INSN_LASX(xvpickev_b, vvv)
INSN_LASX(xvpickev_h, vvv)
INSN_LASX(xvpickev_w, vvv)
INSN_LASX(xvpickev_d, vvv)
INSN_LASX(xvpickod_b, vvv)
INSN_LASX(xvpickod_h, vvv)
INSN_LASX(xvpickod_w, vvv)
INSN_LASX(xvpickod_d, vvv)
INSN_LASX(xvilvl_b, vvv)
INSN_LASX(xvilvl_h, vvv)
INSN_LASX(xvilvl_w, vvv)
INSN_LASX(xvilvl_d, vvv)
INSN_LASX(xvilvh_b, vvv)
INSN_LASX(xvilvh_h, vvv)
INSN_LASX(xvilvh_w, vvv)
INSN_LASX(xvilvh_d, vvv)
INSN_LASX(xvshuf_b, vvvv)
INSN_LASX(xvshuf_h, vvv)
INSN_LASX(xvshuf_w, vvv)
INSN_LASX(xvshuf_d, vvv)
INSN_LASX(xvperm_w, vvv)
INSN_LASX(xvshuf4i_b, vv_i)
INSN_LASX(xvshuf4i_h, vv_i)
INSN_LASX(xvshuf4i_w, vv_i)
INSN_LASX(xvshuf4i_d, vv_i)
INSN_LASX(xvpermi_w, vv_i)
INSN_LASX(xvpermi_d, vv_i)
INSN_LASX(xvpermi_q, vv_i)
INSN_LASX(xvextrins_d, vv_i)
INSN_LASX(xvextrins_w, vv_i)
INSN_LASX(xvextrins_h, vv_i)
INSN_LASX(xvextrins_b, vv_i)
INSN_LASX(xvld, vr_i)
INSN_LASX(xvst, vr_i)
INSN_LASX(xvldx, vrr)
INSN_LASX(xvstx, vrr)
INSN_LASX(xvldrepl_d, vr_i)
INSN_LASX(xvldrepl_w, vr_i)
INSN_LASX(xvldrepl_h, vr_i)
INSN_LASX(xvldrepl_b, vr_i)
INSN_LASX(xvstelm_d, vr_ii)
INSN_LASX(xvstelm_w, vr_ii)
INSN_LASX(xvstelm_h, vr_ii)
INSN_LASX(xvstelm_b, vr_ii)

1
target/loongarch/gdbstub.c
View File

@ -11,6 +11,7 @@
#include "internals.h"
#include "exec/gdbstub.h"
#include "gdbstub/helpers.h"
#include "vec.h"
uint64_t read_fcc(CPULoongArchState *env)
{

631
target/loongarch/helper.h
View File

@ -133,22 +133,22 @@ DEF_HELPER_1(idle, void, env)
#endif
/* LoongArch LSX */
DEF_HELPER_4(vhaddw_h_b, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_w_h, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_d_w, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_q_d, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_hu_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_wu_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_du_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vhaddw_qu_du, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_h_b, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_w_h, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_d_w, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_q_d, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_hu_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_wu_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_du_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vhsubw_qu_du, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vhaddw_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhaddw_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vhsubw_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vaddwev_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vaddwev_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@ -305,22 +305,22 @@ DEF_HELPER_FLAGS_4(vmaddwod_h_bu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vdiv_b, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_h, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_w, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_d, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vdiv_du, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_b, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_h, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_w, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_d, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32)
DEF_HELPER_4(vmod_du, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vdiv_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vdiv_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_bu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_hu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_wu, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmod_du, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsat_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsat_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
@ -331,161 +331,174 @@ DEF_HELPER_FLAGS_4(vsat_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsat_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsat_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_3(vexth_h_b, void, env, i32, i32)
DEF_HELPER_3(vexth_w_h, void, env, i32, i32)
DEF_HELPER_3(vexth_d_w, void, env, i32, i32)
DEF_HELPER_3(vexth_q_d, void, env, i32, i32)
DEF_HELPER_3(vexth_hu_bu, void, env, i32, i32)
DEF_HELPER_3(vexth_wu_hu, void, env, i32, i32)
DEF_HELPER_3(vexth_du_wu, void, env, i32, i32)
DEF_HELPER_3(vexth_qu_du, void, env, i32, i32)
DEF_HELPER_FLAGS_3(vexth_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_w_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_wu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_3(vmskltz_b, void, env, i32, i32)
DEF_HELPER_3(vmskltz_h, void, env, i32, i32)
DEF_HELPER_3(vmskltz_w, void, env, i32, i32)
DEF_HELPER_3(vmskltz_d, void, env, i32, i32)
DEF_HELPER_3(vmskgez_b, void, env, i32, i32)
DEF_HELPER_3(vmsknz_b, void, env, i32,i32)
DEF_HELPER_FLAGS_3(vmskltz_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vmskltz_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vmskltz_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vmskltz_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vmskgez_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vmsknz_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vsllwil_h_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsllwil_w_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsllwil_d_w, void, env, i32, i32, i32)
DEF_HELPER_3(vextl_q_d, void, env, i32, i32)
DEF_HELPER_4(vsllwil_hu_bu, void, env, i32, i32, i32)
DEF_HELPER_4(vsllwil_wu_hu, void, env, i32, i32, i32)
DEF_HELPER_4(vsllwil_du_wu, void, env, i32, i32, i32)
DEF_HELPER_3(vextl_qu_du, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vsllwil_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsllwil_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsllwil_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_3(vextl_q_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsllwil_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsllwil_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsllwil_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_3(vextl_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_4(vsrlr_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlr_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlr_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlr_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlri_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlri_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlri_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlri_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrlr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlr_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlr_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlri_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlri_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlri_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlri_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vsrar_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsrar_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrar_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrar_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrari_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrar_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrar_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrari_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrari_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrari_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrari_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vsrln_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrln_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrln_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsran_w_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrln_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrln_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrln_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsran_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsran_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsran_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vsrlni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrani_d_q, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrlni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrani_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrani_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrani_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrani_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vsrlrn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrn_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarn_w_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrlrn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlrn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrlrn_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrarn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrarn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsrarn_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vsrlrni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrlrni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsrarni_d_q, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsrlrni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlrni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlrni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrlrni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrarni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrarni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrarni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsrarni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vssrln_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssran_wu_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vssrln_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrln_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrln_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrln_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrln_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrln_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssran_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vssrlni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlni_du_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrani_du_q, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vssrlni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrani_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vssrlrn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrn_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrn_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrn_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrn_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarn_wu_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vssrlrn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrlrn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrlrn_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrlrn_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrlrn_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrlrn_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vssrarn_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vssrlrni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_h_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_d_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrlrni_du_q, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_du_q, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vssrlrni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_b_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_h_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_d_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrlrni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_bu_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_hu_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_wu_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vssrarni_du_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_3(vclo_b, void, env, i32, i32)
DEF_HELPER_3(vclo_h, void, env, i32, i32)
DEF_HELPER_3(vclo_w, void, env, i32, i32)
DEF_HELPER_3(vclo_d, void, env, i32, i32)
DEF_HELPER_3(vclz_b, void, env, i32, i32)
DEF_HELPER_3(vclz_h, void, env, i32, i32)
DEF_HELPER_3(vclz_w, void, env, i32, i32)
DEF_HELPER_3(vclz_d, void, env, i32, i32)
DEF_HELPER_FLAGS_3(vclo_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclo_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclo_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclo_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclz_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclz_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclz_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vclz_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_3(vpcnt_b, void, env, i32, i32)
DEF_HELPER_3(vpcnt_h, void, env, i32, i32)
DEF_HELPER_3(vpcnt_w, void, env, i32, i32)
DEF_HELPER_3(vpcnt_d, void, env, i32, i32)
DEF_HELPER_FLAGS_3(vpcnt_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vpcnt_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vpcnt_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vpcnt_d, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclr_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vbitclr_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
@ -514,107 +527,107 @@ DEF_HELPER_FLAGS_4(vbitrevi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitrevi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vbitrevi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vfrstp_b, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstp_h, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_b, void, env, i32, i32, i32)
DEF_HELPER_4(vfrstpi_h, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vfrstp_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vfrstp_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vfrstpi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vfrstpi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vfadd_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfadd_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfsub_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmul_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfdiv_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmul_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmul_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfdiv_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfdiv_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vfmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfmsub_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmadd_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfnmsub_d, void, env, i32, i32, i32, i32)
DEF_HELPER_FLAGS_6(vfmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmadd_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmadd_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmsub_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_6(vfnmsub_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vfmax_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmax_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmin_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfmax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vfmaxa_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmaxa_d, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfmina_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vfmaxa_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmaxa_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmina_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfmina_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_3(vflogb_s, void, env, i32, i32)
DEF_HELPER_3(vflogb_d, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vflogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vflogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_3(vfclass_s, void, env, i32, i32)
DEF_HELPER_3(vfclass_d, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vfclass_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfclass_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_3(vfsqrt_s, void, env, i32, i32)
DEF_HELPER_3(vfsqrt_d, void, env, i32, i32)
DEF_HELPER_3(vfrecip_s, void, env, i32, i32)
DEF_HELPER_3(vfrecip_d, void, env, i32, i32)
DEF_HELPER_3(vfrsqrt_s, void, env, i32, i32)
DEF_HELPER_3(vfrsqrt_d, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vfsqrt_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfsqrt_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrecip_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrecip_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrsqrt_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrsqrt_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_3(vfcvtl_s_h, void, env, i32, i32)
DEF_HELPER_3(vfcvth_s_h, void, env, i32, i32)
DEF_HELPER_3(vfcvtl_d_s, void, env, i32, i32)
DEF_HELPER_3(vfcvth_d_s, void, env, i32, i32)
DEF_HELPER_4(vfcvt_h_s, void, env, i32, i32, i32)
DEF_HELPER_4(vfcvt_s_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vfcvtl_s_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfcvth_s_h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfcvtl_d_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfcvth_d_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfcvt_h_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vfcvt_s_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_3(vfrintrne_s, void, env, i32, i32)
DEF_HELPER_3(vfrintrne_d, void, env, i32, i32)
DEF_HELPER_3(vfrintrz_s, void, env, i32, i32)
DEF_HELPER_3(vfrintrz_d, void, env, i32, i32)
DEF_HELPER_3(vfrintrp_s, void, env, i32, i32)
DEF_HELPER_3(vfrintrp_d, void, env, i32, i32)
DEF_HELPER_3(vfrintrm_s, void, env, i32, i32)
DEF_HELPER_3(vfrintrm_d, void, env, i32, i32)
DEF_HELPER_3(vfrint_s, void, env, i32, i32)
DEF_HELPER_3(vfrint_d, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vfrintrne_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrne_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrz_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrz_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrp_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrp_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrm_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrintrm_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrint_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vfrint_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_3(vftintrne_w_s, void, env, i32, i32)
DEF_HELPER_3(vftintrne_l_d, void, env, i32, i32)
DEF_HELPER_3(vftintrz_w_s, void, env, i32, i32)
DEF_HELPER_3(vftintrz_l_d, void, env, i32, i32)
DEF_HELPER_3(vftintrp_w_s, void, env, i32, i32)
DEF_HELPER_3(vftintrp_l_d, void, env, i32, i32)
DEF_HELPER_3(vftintrm_w_s, void, env, i32, i32)
DEF_HELPER_3(vftintrm_l_d, void, env, i32, i32)
DEF_HELPER_3(vftint_w_s, void, env, i32, i32)
DEF_HELPER_3(vftint_l_d, void, env, i32, i32)
DEF_HELPER_3(vftintrz_wu_s, void, env, i32, i32)
DEF_HELPER_3(vftintrz_lu_d, void, env, i32, i32)
DEF_HELPER_3(vftint_wu_s, void, env, i32, i32)
DEF_HELPER_3(vftint_lu_d, void, env, i32, i32)
DEF_HELPER_4(vftintrne_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrz_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrp_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftintrm_w_d, void, env, i32, i32, i32)
DEF_HELPER_4(vftint_w_d, void, env, i32, i32, i32)
DEF_HELPER_3(vftintrnel_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrneh_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrzl_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrzh_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrpl_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrph_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrml_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintrmh_l_s, void, env, i32, i32)
DEF_HELPER_3(vftintl_l_s, void, env, i32, i32)
DEF_HELPER_3(vftinth_l_s, void, env, i32, i32)
DEF_HELPER_FLAGS_4(vftintrne_w_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrne_l_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrz_w_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrz_l_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrp_w_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrp_l_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrm_w_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrm_l_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftint_w_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftint_l_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrz_wu_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrz_lu_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftint_wu_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftint_lu_d, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrne_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrz_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrp_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftintrm_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vftint_w_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrnel_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrneh_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrzl_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrzh_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrpl_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrph_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrml_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintrmh_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftintl_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vftinth_l_s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_3(vffint_s_w, void, env, i32, i32)
DEF_HELPER_3(vffint_d_l, void, env, i32, i32)
DEF_HELPER_3(vffint_s_wu, void, env, i32, i32)
DEF_HELPER_3(vffint_d_lu, void, env, i32, i32)
DEF_HELPER_3(vffintl_d_w, void, env, i32, i32)
DEF_HELPER_3(vffinth_d_w, void, env, i32, i32)
DEF_HELPER_4(vffint_s_l, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vffint_s_w, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vffint_d_l, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vffint_s_wu, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vffint_d_lu, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vffintl_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vffinth_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_5(vffint_s_l, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_FLAGS_4(vseqi_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vseqi_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
@ -639,61 +652,69 @@ DEF_HELPER_FLAGS_4(vslti_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vslti_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vslti_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_5(vfcmp_c_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_s_s, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_c_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vfcmp_s_d, void, env, i32, i32, i32, i32)
DEF_HELPER_6(vfcmp_c_s, void, env, i32, i32, i32, i32, i32)
DEF_HELPER_6(vfcmp_s_s, void, env, i32, i32, i32, i32, i32)
DEF_HELPER_6(vfcmp_c_d, void, env, i32, i32, i32, i32, i32)
DEF_HELPER_6(vfcmp_s_d, void, env, i32, i32, i32, i32, i32)
DEF_HELPER_FLAGS_4(vbitseli_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_3(vsetanyeqz_b, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_h, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_w, void, env, i32, i32)
DEF_HELPER_3(vsetanyeqz_d, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_b, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_h, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_w, void, env, i32, i32)
DEF_HELPER_3(vsetallnez_d, void, env, i32, i32)
DEF_HELPER_4(vsetanyeqz_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsetanyeqz_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsetanyeqz_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsetanyeqz_d, void, env, i32, i32, i32)
DEF_HELPER_4(vsetallnez_b, void, env, i32, i32, i32)
DEF_HELPER_4(vsetallnez_h, void, env, i32, i32, i32)
DEF_HELPER_4(vsetallnez_w, void, env, i32, i32, i32)
DEF_HELPER_4(vsetallnez_d, void, env, i32, i32, i32)
DEF_HELPER_4(vpackev_b, void, env, i32, i32, i32)
DEF_HELPER_4(vpackev_h, void, env, i32, i32, i32)
DEF_HELPER_4(vpackev_w, void, env, i32, i32, i32)
DEF_HELPER_4(vpackev_d, void, env, i32, i32, i32)
DEF_HELPER_4(vpackod_b, void, env, i32, i32, i32)
DEF_HELPER_4(vpackod_h, void, env, i32, i32, i32)
DEF_HELPER_4(vpackod_w, void, env, i32, i32, i32)
DEF_HELPER_4(vpackod_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(xvinsve0_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvinsve0_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvpickve_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(xvpickve_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vpickev_b, void, env, i32, i32, i32)
DEF_HELPER_4(vpickev_h, void, env, i32, i32, i32)
DEF_HELPER_4(vpickev_w, void, env, i32, i32, i32)
DEF_HELPER_4(vpickev_d, void, env, i32, i32, i32)
DEF_HELPER_4(vpickod_b, void, env, i32, i32, i32)
DEF_HELPER_4(vpickod_h, void, env, i32, i32, i32)
DEF_HELPER_4(vpickod_w, void, env, i32, i32, i32)
DEF_HELPER_4(vpickod_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vpackev_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackev_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackev_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackev_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackod_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackod_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackod_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpackod_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vilvl_b, void, env, i32, i32, i32)
DEF_HELPER_4(vilvl_h, void, env, i32, i32, i32)
DEF_HELPER_4(vilvl_w, void, env, i32, i32, i32)
DEF_HELPER_4(vilvl_d, void, env, i32, i32, i32)
DEF_HELPER_4(vilvh_b, void, env, i32, i32, i32)
DEF_HELPER_4(vilvh_h, void, env, i32, i32, i32)
DEF_HELPER_4(vilvh_w, void, env, i32, i32, i32)
DEF_HELPER_4(vilvh_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vpickev_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickev_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickev_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickev_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickod_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickod_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickod_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpickod_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_5(vshuf_b, void, env, i32, i32, i32, i32)
DEF_HELPER_4(vshuf_h, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf_w, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf_d, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf4i_b, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf4i_h, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf4i_w, void, env, i32, i32, i32)
DEF_HELPER_4(vshuf4i_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vilvl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvl_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvl_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvh_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vilvh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_4(vpermi_w, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_5(vshuf_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vshuf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vshuf_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vshuf_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vshuf4i_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vshuf4i_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vshuf4i_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vshuf4i_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_4(vextrins_b, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_h, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_w, void, env, i32, i32, i32)
DEF_HELPER_4(vextrins_d, void, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(vperm_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vpermi_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vpermi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vpermi_q, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vextrins_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vextrins_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vextrins_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vextrins_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

2379
target/loongarch/insn_trans/trans_lsx.c.inc → target/loongarch/insn_trans/trans_vec.c.inc
View File

File diff suppressed because it is too large Load Diff

782
target/loongarch/insns.decode
View File

@ -550,6 +550,10 @@ dbcl 0000 00000010 10101 ............... @i15
@vr_i8i2 .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s2
@vr_i8i3 .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s1
@vr_i8i4 .... ...... imm2:4 imm:s8 rj:5 vd:5 &vr_ii
@vr_i8i2x .... ........ imm2:2 ........ rj:5 vd:5 &vr_ii imm=%i8s3
@vr_i8i3x .... ....... imm2:3 ........ rj:5 vd:5 &vr_ii imm=%i8s2
@vr_i8i4x .... ...... imm2:4 ........ rj:5 vd:5 &vr_ii imm=%i8s1
@vr_i8i5x .... ..... imm2:5 imm:s8 rj:5 vd:5 &vr_ii
@vrr .... ........ ..... rk:5 rj:5 vd:5 &vrr
@v_i13 .... ........ .. imm:13 vd:5 &v_i
@ -1296,3 +1300,781 @@ vstelm_d 0011 00010001 0 . ........ ..... ..... @vr_i8i1
vstelm_w 0011 00010010 .. ........ ..... ..... @vr_i8i2
vstelm_h 0011 0001010 ... ........ ..... ..... @vr_i8i3
vstelm_b 0011 000110 .... ........ ..... ..... @vr_i8i4
#
# LoongArch LASX instructions
#
xvadd_b 0111 01000000 10100 ..... ..... ..... @vvv
xvadd_h 0111 01000000 10101 ..... ..... ..... @vvv
xvadd_w 0111 01000000 10110 ..... ..... ..... @vvv
xvadd_d 0111 01000000 10111 ..... ..... ..... @vvv
xvadd_q 0111 01010010 11010 ..... ..... ..... @vvv
xvsub_b 0111 01000000 11000 ..... ..... ..... @vvv
xvsub_h 0111 01000000 11001 ..... ..... ..... @vvv
xvsub_w 0111 01000000 11010 ..... ..... ..... @vvv
xvsub_d 0111 01000000 11011 ..... ..... ..... @vvv
xvsub_q 0111 01010010 11011 ..... ..... ..... @vvv
xvaddi_bu 0111 01101000 10100 ..... ..... ..... @vv_ui5
xvaddi_hu 0111 01101000 10101 ..... ..... ..... @vv_ui5
xvaddi_wu 0111 01101000 10110 ..... ..... ..... @vv_ui5
xvaddi_du 0111 01101000 10111 ..... ..... ..... @vv_ui5
xvsubi_bu 0111 01101000 11000 ..... ..... ..... @vv_ui5
xvsubi_hu 0111 01101000 11001 ..... ..... ..... @vv_ui5
xvsubi_wu 0111 01101000 11010 ..... ..... ..... @vv_ui5
xvsubi_du 0111 01101000 11011 ..... ..... ..... @vv_ui5
xvneg_b 0111 01101001 11000 01100 ..... ..... @vv
xvneg_h 0111 01101001 11000 01101 ..... ..... @vv
xvneg_w 0111 01101001 11000 01110 ..... ..... @vv
xvneg_d 0111 01101001 11000 01111 ..... ..... @vv
xvsadd_b 0111 01000100 01100 ..... ..... ..... @vvv
xvsadd_h 0111 01000100 01101 ..... ..... ..... @vvv
xvsadd_w 0111 01000100 01110 ..... ..... ..... @vvv
xvsadd_d 0111 01000100 01111 ..... ..... ..... @vvv
xvsadd_bu 0111 01000100 10100 ..... ..... ..... @vvv
xvsadd_hu 0111 01000100 10101 ..... ..... ..... @vvv
xvsadd_wu 0111 01000100 10110 ..... ..... ..... @vvv
xvsadd_du 0111 01000100 10111 ..... ..... ..... @vvv
xvssub_b 0111 01000100 10000 ..... ..... ..... @vvv
xvssub_h 0111 01000100 10001 ..... ..... ..... @vvv
xvssub_w 0111 01000100 10010 ..... ..... ..... @vvv
xvssub_d 0111 01000100 10011 ..... ..... ..... @vvv
xvssub_bu 0111 01000100 11000 ..... ..... ..... @vvv
xvssub_hu 0111 01000100 11001 ..... ..... ..... @vvv
xvssub_wu 0111 01000100 11010 ..... ..... ..... @vvv
xvssub_du 0111 01000100 11011 ..... ..... ..... @vvv
xvhaddw_h_b 0111 01000101 01000 ..... ..... ..... @vvv
xvhaddw_w_h 0111 01000101 01001 ..... ..... ..... @vvv
xvhaddw_d_w 0111 01000101 01010 ..... ..... ..... @vvv
xvhaddw_q_d 0111 01000101 01011 ..... ..... ..... @vvv
xvhaddw_hu_bu 0111 01000101 10000 ..... ..... ..... @vvv
xvhaddw_wu_hu 0111 01000101 10001 ..... ..... ..... @vvv
xvhaddw_du_wu 0111 01000101 10010 ..... ..... ..... @vvv
xvhaddw_qu_du 0111 01000101 10011 ..... ..... ..... @vvv
xvhsubw_h_b 0111 01000101 01100 ..... ..... ..... @vvv
xvhsubw_w_h 0111 01000101 01101 ..... ..... ..... @vvv
xvhsubw_d_w 0111 01000101 01110 ..... ..... ..... @vvv
xvhsubw_q_d 0111 01000101 01111 ..... ..... ..... @vvv
xvhsubw_hu_bu 0111 01000101 10100 ..... ..... ..... @vvv
xvhsubw_wu_hu 0111 01000101 10101 ..... ..... ..... @vvv
xvhsubw_du_wu 0111 01000101 10110 ..... ..... ..... @vvv
xvhsubw_qu_du 0111 01000101 10111 ..... ..... ..... @vvv
xvaddwev_h_b 0111 01000001 11100 ..... ..... ..... @vvv
xvaddwev_w_h 0111 01000001 11101 ..... ..... ..... @vvv
xvaddwev_d_w 0111 01000001 11110 ..... ..... ..... @vvv
xvaddwev_q_d 0111 01000001 11111 ..... ..... ..... @vvv
xvaddwod_h_b 0111 01000010 00100 ..... ..... ..... @vvv
xvaddwod_w_h 0111 01000010 00101 ..... ..... ..... @vvv
xvaddwod_d_w 0111 01000010 00110 ..... ..... ..... @vvv
xvaddwod_q_d 0111 01000010 00111 ..... ..... ..... @vvv
xvsubwev_h_b 0111 01000010 00000 ..... ..... ..... @vvv
xvsubwev_w_h 0111 01000010 00001 ..... ..... ..... @vvv
xvsubwev_d_w 0111 01000010 00010 ..... ..... ..... @vvv
xvsubwev_q_d 0111 01000010 00011 ..... ..... ..... @vvv
xvsubwod_h_b 0111 01000010 01000 ..... ..... ..... @vvv
xvsubwod_w_h 0111 01000010 01001 ..... ..... ..... @vvv
xvsubwod_d_w 0111 01000010 01010 ..... ..... ..... @vvv
xvsubwod_q_d 0111 01000010 01011 ..... ..... ..... @vvv
xvaddwev_h_bu 0111 01000010 11100 ..... ..... ..... @vvv
xvaddwev_w_hu 0111 01000010 11101 ..... ..... ..... @vvv
xvaddwev_d_wu 0111 01000010 11110 ..... ..... ..... @vvv
xvaddwev_q_du 0111 01000010 11111 ..... ..... ..... @vvv
xvaddwod_h_bu 0111 01000011 00100 ..... ..... ..... @vvv
xvaddwod_w_hu 0111 01000011 00101 ..... ..... ..... @vvv
xvaddwod_d_wu 0111 01000011 00110 ..... ..... ..... @vvv
xvaddwod_q_du 0111 01000011 00111 ..... ..... ..... @vvv
xvsubwev_h_bu 0111 01000011 00000 ..... ..... ..... @vvv
xvsubwev_w_hu 0111 01000011 00001 ..... ..... ..... @vvv
xvsubwev_d_wu 0111 01000011 00010 ..... ..... ..... @vvv
xvsubwev_q_du 0111 01000011 00011 ..... ..... ..... @vvv
xvsubwod_h_bu 0111 01000011 01000 ..... ..... ..... @vvv
xvsubwod_w_hu 0111 01000011 01001 ..... ..... ..... @vvv
xvsubwod_d_wu 0111 01000011 01010 ..... ..... ..... @vvv
xvsubwod_q_du 0111 01000011 01011 ..... ..... ..... @vvv
xvaddwev_h_bu_b 0111 01000011 11100 ..... ..... ..... @vvv
xvaddwev_w_hu_h 0111 01000011 11101 ..... ..... ..... @vvv
xvaddwev_d_wu_w 0111 01000011 11110 ..... ..... ..... @vvv
xvaddwev_q_du_d 0111 01000011 11111 ..... ..... ..... @vvv
xvaddwod_h_bu_b 0111 01000100 00000 ..... ..... ..... @vvv
xvaddwod_w_hu_h 0111 01000100 00001 ..... ..... ..... @vvv
xvaddwod_d_wu_w 0111 01000100 00010 ..... ..... ..... @vvv
xvaddwod_q_du_d 0111 01000100 00011 ..... ..... ..... @vvv
xvavg_b 0111 01000110 01000 ..... ..... ..... @vvv
xvavg_h 0111 01000110 01001 ..... ..... ..... @vvv
xvavg_w 0111 01000110 01010 ..... ..... ..... @vvv
xvavg_d 0111 01000110 01011 ..... ..... ..... @vvv
xvavg_bu 0111 01000110 01100 ..... ..... ..... @vvv
xvavg_hu 0111 01000110 01101 ..... ..... ..... @vvv
xvavg_wu 0111 01000110 01110 ..... ..... ..... @vvv
xvavg_du 0111 01000110 01111 ..... ..... ..... @vvv
xvavgr_b 0111 01000110 10000 ..... ..... ..... @vvv
xvavgr_h 0111 01000110 10001 ..... ..... ..... @vvv
xvavgr_w 0111 01000110 10010 ..... ..... ..... @vvv
xvavgr_d 0111 01000110 10011 ..... ..... ..... @vvv
xvavgr_bu 0111 01000110 10100 ..... ..... ..... @vvv
xvavgr_hu 0111 01000110 10101 ..... ..... ..... @vvv
xvavgr_wu 0111 01000110 10110 ..... ..... ..... @vvv
xvavgr_du 0111 01000110 10111 ..... ..... ..... @vvv
xvabsd_b 0111 01000110 00000 ..... ..... ..... @vvv
xvabsd_h 0111 01000110 00001 ..... ..... ..... @vvv
xvabsd_w 0111 01000110 00010 ..... ..... ..... @vvv
xvabsd_d 0111 01000110 00011 ..... ..... ..... @vvv
xvabsd_bu 0111 01000110 00100 ..... ..... ..... @vvv
xvabsd_hu 0111 01000110 00101 ..... ..... ..... @vvv
xvabsd_wu 0111 01000110 00110 ..... ..... ..... @vvv
xvabsd_du 0111 01000110 00111 ..... ..... ..... @vvv
xvadda_b 0111 01000101 11000 ..... ..... ..... @vvv
xvadda_h 0111 01000101 11001 ..... ..... ..... @vvv
xvadda_w 0111 01000101 11010 ..... ..... ..... @vvv
xvadda_d 0111 01000101 11011 ..... ..... ..... @vvv
xvmax_b 0111 01000111 00000 ..... ..... ..... @vvv
xvmax_h 0111 01000111 00001 ..... ..... ..... @vvv
xvmax_w 0111 01000111 00010 ..... ..... ..... @vvv
xvmax_d 0111 01000111 00011 ..... ..... ..... @vvv
xvmax_bu 0111 01000111 01000 ..... ..... ..... @vvv
xvmax_hu 0111 01000111 01001 ..... ..... ..... @vvv
xvmax_wu 0111 01000111 01010 ..... ..... ..... @vvv
xvmax_du 0111 01000111 01011 ..... ..... ..... @vvv
xvmaxi_b 0111 01101001 00000 ..... ..... ..... @vv_i5
xvmaxi_h 0111 01101001 00001 ..... ..... ..... @vv_i5
xvmaxi_w 0111 01101001 00010 ..... ..... ..... @vv_i5
xvmaxi_d 0111 01101001 00011 ..... ..... ..... @vv_i5
xvmaxi_bu 0111 01101001 01000 ..... ..... ..... @vv_ui5
xvmaxi_hu 0111 01101001 01001 ..... ..... ..... @vv_ui5
xvmaxi_wu 0111 01101001 01010 ..... ..... ..... @vv_ui5
xvmaxi_du 0111 01101001 01011 ..... ..... ..... @vv_ui5
xvmin_b 0111 01000111 00100 ..... ..... ..... @vvv
xvmin_h 0111 01000111 00101 ..... ..... ..... @vvv
xvmin_w 0111 01000111 00110 ..... ..... ..... @vvv
xvmin_d 0111 01000111 00111 ..... ..... ..... @vvv
xvmin_bu 0111 01000111 01100 ..... ..... ..... @vvv
xvmin_hu 0111 01000111 01101 ..... ..... ..... @vvv
xvmin_wu 0111 01000111 01110 ..... ..... ..... @vvv
xvmin_du 0111 01000111 01111 ..... ..... ..... @vvv
xvmini_b 0111 01101001 00100 ..... ..... ..... @vv_i5
xvmini_h 0111 01101001 00101 ..... ..... ..... @vv_i5
xvmini_w 0111 01101001 00110 ..... ..... ..... @vv_i5
xvmini_d 0111 01101001 00111 ..... ..... ..... @vv_i5
xvmini_bu 0111 01101001 01100 ..... ..... ..... @vv_ui5
xvmini_hu 0111 01101001 01101 ..... ..... ..... @vv_ui5
xvmini_wu 0111 01101001 01110 ..... ..... ..... @vv_ui5
xvmini_du 0111 01101001 01111 ..... ..... ..... @vv_ui5
xvmul_b 0111 01001000 01000 ..... ..... ..... @vvv
xvmul_h 0111 01001000 01001 ..... ..... ..... @vvv
xvmul_w 0111 01001000 01010 ..... ..... ..... @vvv
xvmul_d 0111 01001000 01011 ..... ..... ..... @vvv
xvmuh_b 0111 01001000 01100 ..... ..... ..... @vvv
xvmuh_h 0111 01001000 01101 ..... ..... ..... @vvv
xvmuh_w 0111 01001000 01110 ..... ..... ..... @vvv
xvmuh_d 0111 01001000 01111 ..... ..... ..... @vvv
xvmuh_bu 0111 01001000 10000 ..... ..... ..... @vvv
xvmuh_hu 0111 01001000 10001 ..... ..... ..... @vvv
xvmuh_wu 0111 01001000 10010 ..... ..... ..... @vvv
xvmuh_du 0111 01001000 10011 ..... ..... ..... @vvv
xvmulwev_h_b 0111 01001001 00000 ..... ..... ..... @vvv
xvmulwev_w_h 0111 01001001 00001 ..... ..... ..... @vvv
xvmulwev_d_w 0111 01001001 00010 ..... ..... ..... @vvv
xvmulwev_q_d 0111 01001001 00011 ..... ..... ..... @vvv
xvmulwod_h_b 0111 01001001 00100 ..... ..... ..... @vvv
xvmulwod_w_h 0111 01001001 00101 ..... ..... ..... @vvv
xvmulwod_d_w 0111 01001001 00110 ..... ..... ..... @vvv
xvmulwod_q_d 0111 01001001 00111 ..... ..... ..... @vvv
xvmulwev_h_bu 0111 01001001 10000 ..... ..... ..... @vvv
xvmulwev_w_hu 0111 01001001 10001 ..... ..... ..... @vvv
xvmulwev_d_wu 0111 01001001 10010 ..... ..... ..... @vvv
xvmulwev_q_du 0111 01001001 10011 ..... ..... ..... @vvv
xvmulwod_h_bu 0111 01001001 10100 ..... ..... ..... @vvv
xvmulwod_w_hu 0111 01001001 10101 ..... ..... ..... @vvv
xvmulwod_d_wu 0111 01001001 10110 ..... ..... ..... @vvv
xvmulwod_q_du 0111 01001001 10111 ..... ..... ..... @vvv
xvmulwev_h_bu_b 0111 01001010 00000 ..... ..... ..... @vvv
xvmulwev_w_hu_h 0111 01001010 00001 ..... ..... ..... @vvv
xvmulwev_d_wu_w 0111 01001010 00010 ..... ..... ..... @vvv
xvmulwev_q_du_d 0111 01001010 00011 ..... ..... ..... @vvv
xvmulwod_h_bu_b 0111 01001010 00100 ..... ..... ..... @vvv
xvmulwod_w_hu_h 0111 01001010 00101 ..... ..... ..... @vvv
xvmulwod_d_wu_w 0111 01001010 00110 ..... ..... ..... @vvv
xvmulwod_q_du_d 0111 01001010 00111 ..... ..... ..... @vvv
xvmadd_b 0111 01001010 10000 ..... ..... ..... @vvv
xvmadd_h 0111 01001010 10001 ..... ..... ..... @vvv
xvmadd_w 0111 01001010 10010 ..... ..... ..... @vvv
xvmadd_d 0111 01001010 10011 ..... ..... ..... @vvv
xvmsub_b 0111 01001010 10100 ..... ..... ..... @vvv
xvmsub_h 0111 01001010 10101 ..... ..... ..... @vvv
xvmsub_w 0111 01001010 10110 ..... ..... ..... @vvv
xvmsub_d 0111 01001010 10111 ..... ..... ..... @vvv
xvmaddwev_h_b 0111 01001010 11000 ..... ..... ..... @vvv
xvmaddwev_w_h 0111 01001010 11001 ..... ..... ..... @vvv
xvmaddwev_d_w 0111 01001010 11010 ..... ..... ..... @vvv
xvmaddwev_q_d 0111 01001010 11011 ..... ..... ..... @vvv
xvmaddwod_h_b 0111 01001010 11100 ..... ..... ..... @vvv
xvmaddwod_w_h 0111 01001010 11101 ..... ..... ..... @vvv
xvmaddwod_d_w 0111 01001010 11110 ..... ..... ..... @vvv
xvmaddwod_q_d 0111 01001010 11111 ..... ..... ..... @vvv
xvmaddwev_h_bu 0111 01001011 01000 ..... ..... ..... @vvv
xvmaddwev_w_hu 0111 01001011 01001 ..... ..... ..... @vvv
xvmaddwev_d_wu 0111 01001011 01010 ..... ..... ..... @vvv
xvmaddwev_q_du 0111 01001011 01011 ..... ..... ..... @vvv
xvmaddwod_h_bu 0111 01001011 01100 ..... ..... ..... @vvv
xvmaddwod_w_hu 0111 01001011 01101 ..... ..... ..... @vvv
xvmaddwod_d_wu 0111 01001011 01110 ..... ..... ..... @vvv
xvmaddwod_q_du 0111 01001011 01111 ..... ..... ..... @vvv
xvmaddwev_h_bu_b 0111 01001011 11000 ..... ..... ..... @vvv
xvmaddwev_w_hu_h 0111 01001011 11001 ..... ..... ..... @vvv
xvmaddwev_d_wu_w 0111 01001011 11010 ..... ..... ..... @vvv
xvmaddwev_q_du_d 0111 01001011 11011 ..... ..... ..... @vvv
xvmaddwod_h_bu_b 0111 01001011 11100 ..... ..... ..... @vvv
xvmaddwod_w_hu_h 0111 01001011 11101 ..... ..... ..... @vvv
xvmaddwod_d_wu_w 0111 01001011 11110 ..... ..... ..... @vvv
xvmaddwod_q_du_d 0111 01001011 11111 ..... ..... ..... @vvv
xvdiv_b 0111 01001110 00000 ..... ..... ..... @vvv
xvdiv_h 0111 01001110 00001 ..... ..... ..... @vvv
xvdiv_w 0111 01001110 00010 ..... ..... ..... @vvv
xvdiv_d 0111 01001110 00011 ..... ..... ..... @vvv
xvmod_b 0111 01001110 00100 ..... ..... ..... @vvv
xvmod_h 0111 01001110 00101 ..... ..... ..... @vvv
xvmod_w 0111 01001110 00110 ..... ..... ..... @vvv
xvmod_d 0111 01001110 00111 ..... ..... ..... @vvv
xvdiv_bu 0111 01001110 01000 ..... ..... ..... @vvv
xvdiv_hu 0111 01001110 01001 ..... ..... ..... @vvv
xvdiv_wu 0111 01001110 01010 ..... ..... ..... @vvv
xvdiv_du 0111 01001110 01011 ..... ..... ..... @vvv
xvmod_bu 0111 01001110 01100 ..... ..... ..... @vvv
xvmod_hu 0111 01001110 01101 ..... ..... ..... @vvv
xvmod_wu 0111 01001110 01110 ..... ..... ..... @vvv
xvmod_du 0111 01001110 01111 ..... ..... ..... @vvv
xvsat_b 0111 01110010 01000 01 ... ..... ..... @vv_ui3
xvsat_h 0111 01110010 01000 1 .... ..... ..... @vv_ui4
xvsat_w 0111 01110010 01001 ..... ..... ..... @vv_ui5
xvsat_d 0111 01110010 0101 ...... ..... ..... @vv_ui6
xvsat_bu 0111 01110010 10000 01 ... ..... ..... @vv_ui3
xvsat_hu 0111 01110010 10000 1 .... ..... ..... @vv_ui4
xvsat_wu 0111 01110010 10001 ..... ..... ..... @vv_ui5
xvsat_du 0111 01110010 1001 ...... ..... ..... @vv_ui6
xvexth_h_b 0111 01101001 11101 11000 ..... ..... @vv
xvexth_w_h 0111 01101001 11101 11001 ..... ..... @vv
xvexth_d_w 0111 01101001 11101 11010 ..... ..... @vv
xvexth_q_d 0111 01101001 11101 11011 ..... ..... @vv
xvexth_hu_bu 0111 01101001 11101 11100 ..... ..... @vv
xvexth_wu_hu 0111 01101001 11101 11101 ..... ..... @vv
xvexth_du_wu 0111 01101001 11101 11110 ..... ..... @vv
xvexth_qu_du 0111 01101001 11101 11111 ..... ..... @vv
vext2xv_h_b 0111 01101001 11110 00100 ..... ..... @vv
vext2xv_w_b 0111 01101001 11110 00101 ..... ..... @vv
vext2xv_d_b 0111 01101001 11110 00110 ..... ..... @vv
vext2xv_w_h 0111 01101001 11110 00111 ..... ..... @vv
vext2xv_d_h 0111 01101001 11110 01000 ..... ..... @vv
vext2xv_d_w 0111 01101001 11110 01001 ..... ..... @vv
vext2xv_hu_bu 0111 01101001 11110 01010 ..... ..... @vv
vext2xv_wu_bu 0111 01101001 11110 01011 ..... ..... @vv
vext2xv_du_bu 0111 01101001 11110 01100 ..... ..... @vv
vext2xv_wu_hu 0111 01101001 11110 01101 ..... ..... @vv
vext2xv_du_hu 0111 01101001 11110 01110 ..... ..... @vv
vext2xv_du_wu 0111 01101001 11110 01111 ..... ..... @vv
xvsigncov_b 0111 01010010 11100 ..... ..... ..... @vvv
xvsigncov_h 0111 01010010 11101 ..... ..... ..... @vvv
xvsigncov_w 0111 01010010 11110 ..... ..... ..... @vvv
xvsigncov_d 0111 01010010 11111 ..... ..... ..... @vvv
xvmskltz_b 0111 01101001 11000 10000 ..... ..... @vv
xvmskltz_h 0111 01101001 11000 10001 ..... ..... @vv
xvmskltz_w 0111 01101001 11000 10010 ..... ..... @vv
xvmskltz_d 0111 01101001 11000 10011 ..... ..... @vv
xvmskgez_b 0111 01101001 11000 10100 ..... ..... @vv
xvmsknz_b 0111 01101001 11000 11000 ..... ..... @vv
xvldi 0111 01111110 00 ............. ..... @v_i13
xvand_v 0111 01010010 01100 ..... ..... ..... @vvv
xvor_v 0111 01010010 01101 ..... ..... ..... @vvv
xvxor_v 0111 01010010 01110 ..... ..... ..... @vvv
xvnor_v 0111 01010010 01111 ..... ..... ..... @vvv
xvandn_v 0111 01010010 10000 ..... ..... ..... @vvv
xvorn_v 0111 01010010 10001 ..... ..... ..... @vvv
xvandi_b 0111 01111101 00 ........ ..... ..... @vv_ui8
xvori_b 0111 01111101 01 ........ ..... ..... @vv_ui8
xvxori_b 0111 01111101 10 ........ ..... ..... @vv_ui8
xvnori_b 0111 01111101 11 ........ ..... ..... @vv_ui8
xvsll_b 0111 01001110 10000 ..... ..... ..... @vvv
xvsll_h 0111 01001110 10001 ..... ..... ..... @vvv
xvsll_w 0111 01001110 10010 ..... ..... ..... @vvv
xvsll_d 0111 01001110 10011 ..... ..... ..... @vvv
xvslli_b 0111 01110010 11000 01 ... ..... ..... @vv_ui3
xvslli_h 0111 01110010 11000 1 .... ..... ..... @vv_ui4
xvslli_w 0111 01110010 11001 ..... ..... ..... @vv_ui5
xvslli_d 0111 01110010 1101 ...... ..... ..... @vv_ui6
xvsrl_b 0111 01001110 10100 ..... ..... ..... @vvv
xvsrl_h 0111 01001110 10101 ..... ..... ..... @vvv
xvsrl_w 0111 01001110 10110 ..... ..... ..... @vvv
xvsrl_d 0111 01001110 10111 ..... ..... ..... @vvv
xvsrli_b 0111 01110011 00000 01 ... ..... ..... @vv_ui3
xvsrli_h 0111 01110011 00000 1 .... ..... ..... @vv_ui4
xvsrli_w 0111 01110011 00001 ..... ..... ..... @vv_ui5
xvsrli_d 0111 01110011 0001 ...... ..... ..... @vv_ui6
xvsra_b 0111 01001110 11000 ..... ..... ..... @vvv
xvsra_h 0111 01001110 11001 ..... ..... ..... @vvv
xvsra_w 0111 01001110 11010 ..... ..... ..... @vvv
xvsra_d 0111 01001110 11011 ..... ..... ..... @vvv
xvsrai_b 0111 01110011 01000 01 ... ..... ..... @vv_ui3
xvsrai_h 0111 01110011 01000 1 .... ..... ..... @vv_ui4
xvsrai_w 0111 01110011 01001 ..... ..... ..... @vv_ui5
xvsrai_d 0111 01110011 0101 ...... ..... ..... @vv_ui6
xvrotr_b 0111 01001110 11100 ..... ..... ..... @vvv
xvrotr_h 0111 01001110 11101 ..... ..... ..... @vvv
xvrotr_w 0111 01001110 11110 ..... ..... ..... @vvv
xvrotr_d 0111 01001110 11111 ..... ..... ..... @vvv
xvrotri_b 0111 01101010 00000 01 ... ..... ..... @vv_ui3
xvrotri_h 0111 01101010 00000 1 .... ..... ..... @vv_ui4
xvrotri_w 0111 01101010 00001 ..... ..... ..... @vv_ui5
xvrotri_d 0111 01101010 0001 ...... ..... ..... @vv_ui6
xvsllwil_h_b 0111 01110000 10000 01 ... ..... ..... @vv_ui3
xvsllwil_w_h 0111 01110000 10000 1 .... ..... ..... @vv_ui4
xvsllwil_d_w 0111 01110000 10001 ..... ..... ..... @vv_ui5
xvextl_q_d 0111 01110000 10010 00000 ..... ..... @vv
xvsllwil_hu_bu 0111 01110000 11000 01 ... ..... ..... @vv_ui3
xvsllwil_wu_hu 0111 01110000 11000 1 .... ..... ..... @vv_ui4
xvsllwil_du_wu 0111 01110000 11001 ..... ..... ..... @vv_ui5
xvextl_qu_du 0111 01110000 11010 00000 ..... ..... @vv
xvsrlr_b 0111 01001111 00000 ..... ..... ..... @vvv
xvsrlr_h 0111 01001111 00001 ..... ..... ..... @vvv
xvsrlr_w 0111 01001111 00010 ..... ..... ..... @vvv
xvsrlr_d 0111 01001111 00011 ..... ..... ..... @vvv
xvsrlri_b 0111 01101010 01000 01 ... ..... ..... @vv_ui3
xvsrlri_h 0111 01101010 01000 1 .... ..... ..... @vv_ui4
xvsrlri_w 0111 01101010 01001 ..... ..... ..... @vv_ui5
xvsrlri_d 0111 01101010 0101 ...... ..... ..... @vv_ui6
xvsrar_b 0111 01001111 00100 ..... ..... ..... @vvv
xvsrar_h 0111 01001111 00101 ..... ..... ..... @vvv
xvsrar_w 0111 01001111 00110 ..... ..... ..... @vvv
xvsrar_d 0111 01001111 00111 ..... ..... ..... @vvv
xvsrari_b 0111 01101010 10000 01 ... ..... ..... @vv_ui3
xvsrari_h 0111 01101010 10000 1 .... ..... ..... @vv_ui4
xvsrari_w 0111 01101010 10001 ..... ..... ..... @vv_ui5
xvsrari_d 0111 01101010 1001 ...... ..... ..... @vv_ui6
xvsrln_b_h 0111 01001111 01001 ..... ..... ..... @vvv
xvsrln_h_w 0111 01001111 01010 ..... ..... ..... @vvv
xvsrln_w_d 0111 01001111 01011 ..... ..... ..... @vvv
xvsran_b_h 0111 01001111 01101 ..... ..... ..... @vvv
xvsran_h_w 0111 01001111 01110 ..... ..... ..... @vvv
xvsran_w_d 0111 01001111 01111 ..... ..... ..... @vvv
xvsrlni_b_h 0111 01110100 00000 1 .... ..... ..... @vv_ui4
xvsrlni_h_w 0111 01110100 00001 ..... ..... ..... @vv_ui5
xvsrlni_w_d 0111 01110100 0001 ...... ..... ..... @vv_ui6
xvsrlni_d_q 0111 01110100 001 ....... ..... ..... @vv_ui7
xvsrani_b_h 0111 01110101 10000 1 .... ..... ..... @vv_ui4
xvsrani_h_w 0111 01110101 10001 ..... ..... ..... @vv_ui5
xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6
xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7
xvsrlrn_b_h 0111 01001111 10001 ..... ..... ..... @vvv
xvsrlrn_h_w 0111 01001111 10010 ..... ..... ..... @vvv
xvsrlrn_w_d 0111 01001111 10011 ..... ..... ..... @vvv
xvsrarn_b_h 0111 01001111 10101 ..... ..... ..... @vvv
xvsrarn_h_w 0111 01001111 10110 ..... ..... ..... @vvv
xvsrarn_w_d 0111 01001111 10111 ..... ..... ..... @vvv
xvsrlrni_b_h 0111 01110100 01000 1 .... ..... ..... @vv_ui4
xvsrlrni_h_w 0111 01110100 01001 ..... ..... ..... @vv_ui5
xvsrlrni_w_d 0111 01110100 0101 ...... ..... ..... @vv_ui6
xvsrlrni_d_q 0111 01110100 011 ....... ..... ..... @vv_ui7
xvsrarni_b_h 0111 01110101 11000 1 .... ..... ..... @vv_ui4
xvsrarni_h_w 0111 01110101 11001 ..... ..... ..... @vv_ui5
xvsrarni_w_d 0111 01110101 1101 ...... ..... ..... @vv_ui6
xvsrarni_d_q 0111 01110101 111 ....... ..... ..... @vv_ui7
xvssrln_b_h 0111 01001111 11001 ..... ..... ..... @vvv
xvssrln_h_w 0111 01001111 11010 ..... ..... ..... @vvv
xvssrln_w_d 0111 01001111 11011 ..... ..... ..... @vvv
xvssran_b_h 0111 01001111 11101 ..... ..... ..... @vvv
xvssran_h_w 0111 01001111 11110 ..... ..... ..... @vvv
xvssran_w_d 0111 01001111 11111 ..... ..... ..... @vvv
xvssrln_bu_h 0111 01010000 01001 ..... ..... ..... @vvv
xvssrln_hu_w 0111 01010000 01010 ..... ..... ..... @vvv
xvssrln_wu_d 0111 01010000 01011 ..... ..... ..... @vvv
xvssran_bu_h 0111 01010000 01101 ..... ..... ..... @vvv
xvssran_hu_w 0111 01010000 01110 ..... ..... ..... @vvv
xvssran_wu_d 0111 01010000 01111 ..... ..... ..... @vvv
xvssrlni_b_h 0111 01110100 10000 1 .... ..... ..... @vv_ui4
xvssrlni_h_w 0111 01110100 10001 ..... ..... ..... @vv_ui5
xvssrlni_w_d 0111 01110100 1001 ...... ..... ..... @vv_ui6
xvssrlni_d_q 0111 01110100 101 ....... ..... ..... @vv_ui7
xvssrani_b_h 0111 01110110 00000 1 .... ..... ..... @vv_ui4
xvssrani_h_w 0111 01110110 00001 ..... ..... ..... @vv_ui5
xvssrani_w_d 0111 01110110 0001 ...... ..... ..... @vv_ui6
xvssrani_d_q 0111 01110110 001 ....... ..... ..... @vv_ui7
xvssrlni_bu_h 0111 01110100 11000 1 .... ..... ..... @vv_ui4
xvssrlni_hu_w 0111 01110100 11001 ..... ..... ..... @vv_ui5
xvssrlni_wu_d 0111 01110100 1101 ...... ..... ..... @vv_ui6
xvssrlni_du_q 0111 01110100 111 ....... ..... ..... @vv_ui7
xvssrani_bu_h 0111 01110110 01000 1 .... ..... ..... @vv_ui4
xvssrani_hu_w 0111 01110110 01001 ..... ..... ..... @vv_ui5
xvssrani_wu_d 0111 01110110 0101 ...... ..... ..... @vv_ui6
xvssrani_du_q 0111 01110110 011 ....... ..... ..... @vv_ui7
xvssrlrn_b_h 0111 01010000 00001 ..... ..... ..... @vvv
xvssrlrn_h_w 0111 01010000 00010 ..... ..... ..... @vvv
xvssrlrn_w_d 0111 01010000 00011 ..... ..... ..... @vvv
xvssrarn_b_h 0111 01010000 00101 ..... ..... ..... @vvv
xvssrarn_h_w 0111 01010000 00110 ..... ..... ..... @vvv
xvssrarn_w_d 0111 01010000 00111 ..... ..... ..... @vvv
xvssrlrn_bu_h 0111 01010000 10001 ..... ..... ..... @vvv
xvssrlrn_hu_w 0111 01010000 10010 ..... ..... ..... @vvv
xvssrlrn_wu_d 0111 01010000 10011 ..... ..... ..... @vvv
xvssrarn_bu_h 0111 01010000 10101 ..... ..... ..... @vvv
xvssrarn_hu_w 0111 01010000 10110 ..... ..... ..... @vvv
xvssrarn_wu_d 0111 01010000 10111 ..... ..... ..... @vvv
xvssrlrni_b_h 0111 01110101 00000 1 .... ..... ..... @vv_ui4
xvssrlrni_h_w 0111 01110101 00001 ..... ..... ..... @vv_ui5
xvssrlrni_w_d 0111 01110101 0001 ...... ..... ..... @vv_ui6
xvssrlrni_d_q 0111 01110101 001 ....... ..... ..... @vv_ui7
xvssrarni_b_h 0111 01110110 10000 1 .... ..... ..... @vv_ui4
xvssrarni_h_w 0111 01110110 10001 ..... ..... ..... @vv_ui5
xvssrarni_w_d 0111 01110110 1001 ...... ..... ..... @vv_ui6
xvssrarni_d_q 0111 01110110 101 ....... ..... ..... @vv_ui7
xvssrlrni_bu_h 0111 01110101 01000 1 .... ..... ..... @vv_ui4
xvssrlrni_hu_w 0111 01110101 01001 ..... ..... ..... @vv_ui5
xvssrlrni_wu_d 0111 01110101 0101 ...... ..... ..... @vv_ui6
xvssrlrni_du_q 0111 01110101 011 ....... ..... ..... @vv_ui7
xvssrarni_bu_h 0111 01110110 11000 1 .... ..... ..... @vv_ui4
xvssrarni_hu_w 0111 01110110 11001 ..... ..... ..... @vv_ui5
xvssrarni_wu_d 0111 01110110 1101 ...... ..... ..... @vv_ui6
xvssrarni_du_q 0111 01110110 111 ....... ..... ..... @vv_ui7
xvclo_b 0111 01101001 11000 00000 ..... ..... @vv
xvclo_h 0111 01101001 11000 00001 ..... ..... @vv
xvclo_w 0111 01101001 11000 00010 ..... ..... @vv
xvclo_d 0111 01101001 11000 00011 ..... ..... @vv
xvclz_b 0111 01101001 11000 00100 ..... ..... @vv
xvclz_h 0111 01101001 11000 00101 ..... ..... @vv
xvclz_w 0111 01101001 11000 00110 ..... ..... @vv
xvclz_d 0111 01101001 11000 00111 ..... ..... @vv
xvpcnt_b 0111 01101001 11000 01000 ..... ..... @vv
xvpcnt_h 0111 01101001 11000 01001 ..... ..... @vv
xvpcnt_w 0111 01101001 11000 01010 ..... ..... @vv
xvpcnt_d 0111 01101001 11000 01011 ..... ..... @vv
xvbitclr_b 0111 01010000 11000 ..... ..... ..... @vvv
xvbitclr_h 0111 01010000 11001 ..... ..... ..... @vvv
xvbitclr_w 0111 01010000 11010 ..... ..... ..... @vvv
xvbitclr_d 0111 01010000 11011 ..... ..... ..... @vvv
xvbitclri_b 0111 01110001 00000 01 ... ..... ..... @vv_ui3
xvbitclri_h 0111 01110001 00000 1 .... ..... ..... @vv_ui4
xvbitclri_w 0111 01110001 00001 ..... ..... ..... @vv_ui5
xvbitclri_d 0111 01110001 0001 ...... ..... ..... @vv_ui6
xvbitset_b 0111 01010000 11100 ..... ..... ..... @vvv
xvbitset_h 0111 01010000 11101 ..... ..... ..... @vvv
xvbitset_w 0111 01010000 11110 ..... ..... ..... @vvv
xvbitset_d 0111 01010000 11111 ..... ..... ..... @vvv
xvbitseti_b 0111 01110001 01000 01 ... ..... ..... @vv_ui3
xvbitseti_h 0111 01110001 01000 1 .... ..... ..... @vv_ui4
xvbitseti_w 0111 01110001 01001 ..... ..... ..... @vv_ui5
xvbitseti_d 0111 01110001 0101 ...... ..... ..... @vv_ui6
xvbitrev_b 0111 01010001 00000 ..... ..... ..... @vvv
xvbitrev_h 0111 01010001 00001 ..... ..... ..... @vvv
xvbitrev_w 0111 01010001 00010 ..... ..... ..... @vvv
xvbitrev_d 0111 01010001 00011 ..... ..... ..... @vvv
xvbitrevi_b 0111 01110001 10000 01 ... ..... ..... @vv_ui3
xvbitrevi_h 0111 01110001 10000 1 .... ..... ..... @vv_ui4
xvbitrevi_w 0111 01110001 10001 ..... ..... ..... @vv_ui5
xvbitrevi_d 0111 01110001 1001 ...... ..... ..... @vv_ui6
xvfrstp_b 0111 01010010 10110 ..... ..... ..... @vvv
xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
xvfadd_s 0111 01010011 00001 ..... ..... ..... @vvv
xvfadd_d 0111 01010011 00010 ..... ..... ..... @vvv
xvfsub_s 0111 01010011 00101 ..... ..... ..... @vvv
xvfsub_d 0111 01010011 00110 ..... ..... ..... @vvv
xvfmul_s 0111 01010011 10001 ..... ..... ..... @vvv
xvfmul_d 0111 01010011 10010 ..... ..... ..... @vvv
xvfdiv_s 0111 01010011 10101 ..... ..... ..... @vvv
xvfdiv_d 0111 01010011 10110 ..... ..... ..... @vvv
xvfmadd_s 0000 10100001 ..... ..... ..... ..... @vvvv
xvfmadd_d 0000 10100010 ..... ..... ..... ..... @vvvv
xvfmsub_s 0000 10100101 ..... ..... ..... ..... @vvvv
xvfmsub_d 0000 10100110 ..... ..... ..... ..... @vvvv
xvfnmadd_s 0000 10101001 ..... ..... ..... ..... @vvvv
xvfnmadd_d 0000 10101010 ..... ..... ..... ..... @vvvv
xvfnmsub_s 0000 10101101 ..... ..... ..... ..... @vvvv
xvfnmsub_d 0000 10101110 ..... ..... ..... ..... @vvvv
xvfmax_s 0111 01010011 11001 ..... ..... ..... @vvv
xvfmax_d 0111 01010011 11010 ..... ..... ..... @vvv
xvfmin_s 0111 01010011 11101 ..... ..... ..... @vvv
xvfmin_d 0111 01010011 11110 ..... ..... ..... @vvv
xvfmaxa_s 0111 01010100 00001 ..... ..... ..... @vvv
xvfmaxa_d 0111 01010100 00010 ..... ..... ..... @vvv
xvfmina_s 0111 01010100 00101 ..... ..... ..... @vvv
xvfmina_d 0111 01010100 00110 ..... ..... ..... @vvv
xvflogb_s 0111 01101001 11001 10001 ..... ..... @vv
xvflogb_d 0111 01101001 11001 10010 ..... ..... @vv
xvfclass_s 0111 01101001 11001 10101 ..... ..... @vv
xvfclass_d 0111 01101001 11001 10110 ..... ..... @vv
xvfsqrt_s 0111 01101001 11001 11001 ..... ..... @vv
xvfsqrt_d 0111 01101001 11001 11010 ..... ..... @vv
xvfrecip_s 0111 01101001 11001 11101 ..... ..... @vv
xvfrecip_d 0111 01101001 11001 11110 ..... ..... @vv
xvfrsqrt_s 0111 01101001 11010 00001 ..... ..... @vv
xvfrsqrt_d 0111 01101001 11010 00010 ..... ..... @vv
xvfcvtl_s_h 0111 01101001 11011 11010 ..... ..... @vv
xvfcvth_s_h 0111 01101001 11011 11011 ..... ..... @vv
xvfcvtl_d_s 0111 01101001 11011 11100 ..... ..... @vv
xvfcvth_d_s 0111 01101001 11011 11101 ..... ..... @vv
xvfcvt_h_s 0111 01010100 01100 ..... ..... ..... @vvv
xvfcvt_s_d 0111 01010100 01101 ..... ..... ..... @vvv
xvfrintrne_s 0111 01101001 11010 11101 ..... ..... @vv
xvfrintrne_d 0111 01101001 11010 11110 ..... ..... @vv
xvfrintrz_s 0111 01101001 11010 11001 ..... ..... @vv
xvfrintrz_d 0111 01101001 11010 11010 ..... ..... @vv
xvfrintrp_s 0111 01101001 11010 10101 ..... ..... @vv
xvfrintrp_d 0111 01101001 11010 10110 ..... ..... @vv
xvfrintrm_s 0111 01101001 11010 10001 ..... ..... @vv
xvfrintrm_d 0111 01101001 11010 10010 ..... ..... @vv
xvfrint_s 0111 01101001 11010 01101 ..... ..... @vv
xvfrint_d 0111 01101001 11010 01110 ..... ..... @vv
xvftintrne_w_s 0111 01101001 11100 10100 ..... ..... @vv
xvftintrne_l_d 0111 01101001 11100 10101 ..... ..... @vv
xvftintrz_w_s 0111 01101001 11100 10010 ..... ..... @vv
xvftintrz_l_d 0111 01101001 11100 10011 ..... ..... @vv
xvftintrp_w_s 0111 01101001 11100 10000 ..... ..... @vv
xvftintrp_l_d 0111 01101001 11100 10001 ..... ..... @vv
xvftintrm_w_s 0111 01101001 11100 01110 ..... ..... @vv
xvftintrm_l_d 0111 01101001 11100 01111 ..... ..... @vv
xvftint_w_s 0111 01101001 11100 01100 ..... ..... @vv
xvftint_l_d 0111 01101001 11100 01101 ..... ..... @vv
xvftintrz_wu_s 0111 01101001 11100 11100 ..... ..... @vv
xvftintrz_lu_d 0111 01101001 11100 11101 ..... ..... @vv
xvftint_wu_s 0111 01101001 11100 10110 ..... ..... @vv
xvftint_lu_d 0111 01101001 11100 10111 ..... ..... @vv
xvftintrne_w_d 0111 01010100 10111 ..... ..... ..... @vvv
xvftintrz_w_d 0111 01010100 10110 ..... ..... ..... @vvv
xvftintrp_w_d 0111 01010100 10101 ..... ..... ..... @vvv
xvftintrm_w_d 0111 01010100 10100 ..... ..... ..... @vvv
xvftint_w_d 0111 01010100 10011 ..... ..... ..... @vvv
xvftintrnel_l_s 0111 01101001 11101 01000 ..... ..... @vv
xvftintrneh_l_s 0111 01101001 11101 01001 ..... ..... @vv
xvftintrzl_l_s 0111 01101001 11101 00110 ..... ..... @vv
xvftintrzh_l_s 0111 01101001 11101 00111 ..... ..... @vv
xvftintrpl_l_s 0111 01101001 11101 00100 ..... ..... @vv
xvftintrph_l_s 0111 01101001 11101 00101 ..... ..... @vv
xvftintrml_l_s 0111 01101001 11101 00010 ..... ..... @vv
xvftintrmh_l_s 0111 01101001 11101 00011 ..... ..... @vv
xvftintl_l_s 0111 01101001 11101 00000 ..... ..... @vv
xvftinth_l_s 0111 01101001 11101 00001 ..... ..... @vv
xvffint_s_w 0111 01101001 11100 00000 ..... ..... @vv
xvffint_d_l 0111 01101001 11100 00010 ..... ..... @vv
xvffint_s_wu 0111 01101001 11100 00001 ..... ..... @vv
xvffint_d_lu 0111 01101001 11100 00011 ..... ..... @vv
xvffintl_d_w 0111 01101001 11100 00100 ..... ..... @vv
xvffinth_d_w 0111 01101001 11100 00101 ..... ..... @vv
xvffint_s_l 0111 01010100 10000 ..... ..... ..... @vvv
xvseq_b 0111 01000000 00000 ..... ..... ..... @vvv
xvseq_h 0111 01000000 00001 ..... ..... ..... @vvv
xvseq_w 0111 01000000 00010 ..... ..... ..... @vvv
xvseq_d 0111 01000000 00011 ..... ..... ..... @vvv
xvseqi_b 0111 01101000 00000 ..... ..... ..... @vv_i5
xvseqi_h 0111 01101000 00001 ..... ..... ..... @vv_i5
xvseqi_w 0111 01101000 00010 ..... ..... ..... @vv_i5
xvseqi_d 0111 01101000 00011 ..... ..... ..... @vv_i5
xvsle_b 0111 01000000 00100 ..... ..... ..... @vvv
xvsle_h 0111 01000000 00101 ..... ..... ..... @vvv
xvsle_w 0111 01000000 00110 ..... ..... ..... @vvv
xvsle_d 0111 01000000 00111 ..... ..... ..... @vvv
xvslei_b 0111 01101000 00100 ..... ..... ..... @vv_i5
xvslei_h 0111 01101000 00101 ..... ..... ..... @vv_i5
xvslei_w 0111 01101000 00110 ..... ..... ..... @vv_i5
xvslei_d 0111 01101000 00111 ..... ..... ..... @vv_i5
xvsle_bu 0111 01000000 01000 ..... ..... ..... @vvv
xvsle_hu 0111 01000000 01001 ..... ..... ..... @vvv
xvsle_wu 0111 01000000 01010 ..... ..... ..... @vvv
xvsle_du 0111 01000000 01011 ..... ..... ..... @vvv
xvslei_bu 0111 01101000 01000 ..... ..... ..... @vv_ui5
xvslei_hu 0111 01101000 01001 ..... ..... ..... @vv_ui5
xvslei_wu 0111 01101000 01010 ..... ..... ..... @vv_ui5
xvslei_du 0111 01101000 01011 ..... ..... ..... @vv_ui5
xvslt_b 0111 01000000 01100 ..... ..... ..... @vvv
xvslt_h 0111 01000000 01101 ..... ..... ..... @vvv
xvslt_w 0111 01000000 01110 ..... ..... ..... @vvv
xvslt_d 0111 01000000 01111 ..... ..... ..... @vvv
xvslti_b 0111 01101000 01100 ..... ..... ..... @vv_i5
xvslti_h 0111 01101000 01101 ..... ..... ..... @vv_i5
xvslti_w 0111 01101000 01110 ..... ..... ..... @vv_i5
xvslti_d 0111 01101000 01111 ..... ..... ..... @vv_i5
xvslt_bu 0111 01000000 10000 ..... ..... ..... @vvv
xvslt_hu 0111 01000000 10001 ..... ..... ..... @vvv
xvslt_wu 0111 01000000 10010 ..... ..... ..... @vvv
xvslt_du 0111 01000000 10011 ..... ..... ..... @vvv
xvslti_bu 0111 01101000 10000 ..... ..... ..... @vv_ui5
xvslti_hu 0111 01101000 10001 ..... ..... ..... @vv_ui5
xvslti_wu 0111 01101000 10010 ..... ..... ..... @vv_ui5
xvslti_du 0111 01101000 10011 ..... ..... ..... @vv_ui5
xvfcmp_cond_s 0000 11001001 ..... ..... ..... ..... @vvv_fcond
xvfcmp_cond_d 0000 11001010 ..... ..... ..... ..... @vvv_fcond
xvbitsel_v 0000 11010010 ..... ..... ..... ..... @vvvv
xvbitseli_b 0111 01111100 01 ........ ..... ..... @vv_ui8
xvseteqz_v 0111 01101001 11001 00110 ..... 00 ... @cv
xvsetnez_v 0111 01101001 11001 00111 ..... 00 ... @cv
xvsetanyeqz_b 0111 01101001 11001 01000 ..... 00 ... @cv
xvsetanyeqz_h 0111 01101001 11001 01001 ..... 00 ... @cv
xvsetanyeqz_w 0111 01101001 11001 01010 ..... 00 ... @cv
xvsetanyeqz_d 0111 01101001 11001 01011 ..... 00 ... @cv
xvsetallnez_b 0111 01101001 11001 01100 ..... 00 ... @cv
xvsetallnez_h 0111 01101001 11001 01101 ..... 00 ... @cv
xvsetallnez_w 0111 01101001 11001 01110 ..... 00 ... @cv
xvsetallnez_d 0111 01101001 11001 01111 ..... 00 ... @cv
xvinsgr2vr_w 0111 01101110 10111 10 ... ..... ..... @vr_ui3
xvinsgr2vr_d 0111 01101110 10111 110 .. ..... ..... @vr_ui2
xvpickve2gr_w 0111 01101110 11111 10 ... ..... ..... @rv_ui3
xvpickve2gr_d 0111 01101110 11111 110 .. ..... ..... @rv_ui2
xvpickve2gr_wu 0111 01101111 00111 10 ... ..... ..... @rv_ui3
xvpickve2gr_du 0111 01101111 00111 110 .. ..... ..... @rv_ui2
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
xvreplgr2vr_d 0111 01101001 11110 00011 ..... ..... @vr
xvreplve_b 0111 01010010 00100 ..... ..... ..... @vvr
xvreplve_h 0111 01010010 00101 ..... ..... ..... @vvr
xvreplve_w 0111 01010010 00110 ..... ..... ..... @vvr
xvreplve_d 0111 01010010 00111 ..... ..... ..... @vvr
xvrepl128vei_b 0111 01101111 01111 0 .... ..... ..... @vv_ui4
xvrepl128vei_h 0111 01101111 01111 10 ... ..... ..... @vv_ui3
xvrepl128vei_w 0111 01101111 01111 110 .. ..... ..... @vv_ui2
xvrepl128vei_d 0111 01101111 01111 1110 . ..... ..... @vv_ui1
xvreplve0_b 0111 01110000 01110 00000 ..... ..... @vv
xvreplve0_h 0111 01110000 01111 00000 ..... ..... @vv
xvreplve0_w 0111 01110000 01111 10000 ..... ..... @vv
xvreplve0_d 0111 01110000 01111 11000 ..... ..... @vv
xvreplve0_q 0111 01110000 01111 11100 ..... ..... @vv
xvinsve0_w 0111 01101111 11111 10 ... ..... ..... @vv_ui3
xvinsve0_d 0111 01101111 11111 110 .. ..... ..... @vv_ui2
xvpickve_w 0111 01110000 00111 10 ... ..... ..... @vv_ui3
xvpickve_d 0111 01110000 00111 110 .. ..... ..... @vv_ui2
xvbsll_v 0111 01101000 11100 ..... ..... ..... @vv_ui5
xvbsrl_v 0111 01101000 11101 ..... ..... ..... @vv_ui5
xvpackev_b 0111 01010001 01100 ..... ..... ..... @vvv
xvpackev_h 0111 01010001 01101 ..... ..... ..... @vvv
xvpackev_w 0111 01010001 01110 ..... ..... ..... @vvv
xvpackev_d 0111 01010001 01111 ..... ..... ..... @vvv
xvpackod_b 0111 01010001 10000 ..... ..... ..... @vvv
xvpackod_h 0111 01010001 10001 ..... ..... ..... @vvv
xvpackod_w 0111 01010001 10010 ..... ..... ..... @vvv
xvpackod_d 0111 01010001 10011 ..... ..... ..... @vvv
xvpickev_b 0111 01010001 11100 ..... ..... ..... @vvv
xvpickev_h 0111 01010001 11101 ..... ..... ..... @vvv
xvpickev_w 0111 01010001 11110 ..... ..... ..... @vvv
xvpickev_d 0111 01010001 11111 ..... ..... ..... @vvv
xvpickod_b 0111 01010010 00000 ..... ..... ..... @vvv
xvpickod_h 0111 01010010 00001 ..... ..... ..... @vvv
xvpickod_w 0111 01010010 00010 ..... ..... ..... @vvv
xvpickod_d 0111 01010010 00011 ..... ..... ..... @vvv
xvilvl_b 0111 01010001 10100 ..... ..... ..... @vvv
xvilvl_h 0111 01010001 10101 ..... ..... ..... @vvv
xvilvl_w 0111 01010001 10110 ..... ..... ..... @vvv
xvilvl_d 0111 01010001 10111 ..... ..... ..... @vvv
xvilvh_b 0111 01010001 11000 ..... ..... ..... @vvv
xvilvh_h 0111 01010001 11001 ..... ..... ..... @vvv
xvilvh_w 0111 01010001 11010 ..... ..... ..... @vvv
xvilvh_d 0111 01010001 11011 ..... ..... ..... @vvv
xvshuf_b 0000 11010110 ..... ..... ..... ..... @vvvv
xvshuf_h 0111 01010111 10101 ..... ..... ..... @vvv
xvshuf_w 0111 01010111 10110 ..... ..... ..... @vvv
xvshuf_d 0111 01010111 10111 ..... ..... ..... @vvv
xvperm_w 0111 01010111 11010 ..... ..... ..... @vvv
xvshuf4i_b 0111 01111001 00 ........ ..... ..... @vv_ui8
xvshuf4i_h 0111 01111001 01 ........ ..... ..... @vv_ui8
xvshuf4i_w 0111 01111001 10 ........ ..... ..... @vv_ui8
xvshuf4i_d 0111 01111001 11 ........ ..... ..... @vv_ui8
xvpermi_w 0111 01111110 01 ........ ..... ..... @vv_ui8
xvpermi_d 0111 01111110 10 ........ ..... ..... @vv_ui8
xvpermi_q 0111 01111110 11 ........ ..... ..... @vv_ui8
xvextrins_d 0111 01111000 00 ........ ..... ..... @vv_ui8
xvextrins_w 0111 01111000 01 ........ ..... ..... @vv_ui8
xvextrins_h 0111 01111000 10 ........ ..... ..... @vv_ui8
xvextrins_b 0111 01111000 11 ........ ..... ..... @vv_ui8
xvld 0010 110010 ............ ..... ..... @vr_i12
xvst 0010 110011 ............ ..... ..... @vr_i12
xvldx 0011 10000100 10000 ..... ..... ..... @vrr
xvstx 0011 10000100 11000 ..... ..... ..... @vrr
xvldrepl_d 0011 00100001 0 ......... ..... ..... @vr_i9
xvldrepl_w 0011 00100010 .......... ..... ..... @vr_i10
xvldrepl_h 0011 0010010 ........... ..... ..... @vr_i11
xvldrepl_b 0011 001010 ............ ..... ..... @vr_i12
xvstelm_d 0011 00110001 .. ........ ..... ..... @vr_i8i2x
xvstelm_w 0011 0011001 ... ........ ..... ..... @vr_i8i3x
xvstelm_h 0011 001101 .... ........ ..... ..... @vr_i8i4x
xvstelm_b 0011 00111 ..... ........ ..... ..... @vr_i8i5x

22
target/loongarch/internals.h
View File

@ -21,28 +21,6 @@
/* Global bit for huge page */
#define LOONGARCH_HGLOBAL_SHIFT 12
#if HOST_BIG_ENDIAN
#define B(x) B[15 - (x)]
#define H(x) H[7 - (x)]
#define W(x) W[3 - (x)]
#define D(x) D[1 - (x)]
#define UB(x) UB[15 - (x)]
#define UH(x) UH[7 - (x)]
#define UW(x) UW[3 - (x)]
#define UD(x) UD[1 -(x)]
#define Q(x) Q[x]
#else
#define B(x) B[x]
#define H(x) H[x]
#define W(x) W[x]
#define D(x) D[x]
#define UB(x) UB[x]
#define UH(x) UH[x]
#define UW(x) UW[x]
#define UD(x) UD[x]
#define Q(x) Q[x]
#endif
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);

3004
target/loongarch/lsx_helper.c
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File diff suppressed because it is too large Load Diff

36
target/loongarch/machine.c
View File

@ -8,7 +8,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "migration/cpu.h"
#include "internals.h"
#include "vec.h"
static const VMStateDescription vmstate_fpu_reg = {
.name = "fpu_reg",
@ -76,6 +76,39 @@ static const VMStateDescription vmstate_lsx = {
},
};
static const VMStateDescription vmstate_lasxh_reg = {
.name = "lasxh_reg",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT64(UD(2), VReg),
VMSTATE_UINT64(UD(3), VReg),
VMSTATE_END_OF_LIST()
}
};
#define VMSTATE_LASXH_REGS(_field, _state, _start) \
VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, 32, 0, \
vmstate_lasxh_reg, fpr_t)
static bool lasx_needed(void *opaque)
{
LoongArchCPU *cpu = opaque;
return FIELD_EX64(cpu->env.cpucfg[2], CPUCFG2, LASX);
}
static const VMStateDescription vmstate_lasx = {
.name = "cpu/lasx",
.version_id = 1,
.minimum_version_id = 1,
.needed = lasx_needed,
.fields = (VMStateField[]) {
VMSTATE_LASXH_REGS(env.fpr, LoongArchCPU, 0),
VMSTATE_END_OF_LIST()
},
};
/* TLB state */
const VMStateDescription vmstate_tlb = {
.name = "cpu/tlb",
@ -163,6 +196,7 @@ const VMStateDescription vmstate_loongarch_cpu = {
.subsections = (const VMStateDescription*[]) {
&vmstate_fpu,
&vmstate_lsx,
&vmstate_lasx,
NULL
}
};

2
target/loongarch/meson.build
View File

@ -11,7 +11,7 @@ loongarch_tcg_ss.add(files(
'op_helper.c',
'translate.c',
'gdbstub.c',
'lsx_helper.c',
'vec_helper.c',
))
loongarch_tcg_ss.add(zlib)

19
target/loongarch/translate.c
View File

@ -18,6 +18,7 @@
#include "fpu/softfloat.h"
#include "translate.h"
#include "internals.h"
#include "vec.h"
/* Global register indices */
TCGv cpu_gpr[32], cpu_pc;
@ -36,6 +37,18 @@ static inline int vec_full_offset(int regno)
return offsetof(CPULoongArchState, fpr[regno]);
}
static inline int vec_reg_offset(int regno, int index, MemOp mop)
{
const uint8_t size = 1 << mop;
int offs = index * size;
if (HOST_BIG_ENDIAN && size < 8 ) {
offs ^= (8 - size);
}
return offs + vec_full_offset(regno);
}
static inline void get_vreg64(TCGv_i64 dest, int regno, int index)
{
tcg_gen_ld_i64(dest, cpu_env,
@ -123,6 +136,10 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
ctx->vl = LSX_LEN;
}
if (FIELD_EX64(env->cpucfg[2], CPUCFG2, LASX)) {
ctx->vl = LASX_LEN;
}
ctx->la64 = is_la64(env);
ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
@ -261,7 +278,7 @@ static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr)
#include "insn_trans/trans_fmemory.c.inc"
#include "insn_trans/trans_branch.c.inc"
#include "insn_trans/trans_privileged.c.inc"
#include "insn_trans/trans_lsx.c.inc"
#include "insn_trans/trans_vec.c.inc"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{

1
target/loongarch/translate.h
View File

@ -23,6 +23,7 @@
#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))
#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))
#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))
#define avail_LASX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LASX))
#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR))
/*

75
target/loongarch/vec.h Normal file
View File

@ -0,0 +1,75 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU LoongArch vector utilitites
*
* Copyright (c) 2023 Loongson Technology Corporation Limited
*/
#ifndef LOONGARCH_VEC_H
#define LOONGARCH_VEC_H
#if HOST_BIG_ENDIAN
#define B(x) B[(x) ^ 15]
#define H(x) H[(x) ^ 7]
#define W(x) W[(x) ^ 3]
#define D(x) D[(x) ^ 1]
#define UB(x) UB[(x) ^ 15]
#define UH(x) UH[(x) ^ 7]
#define UW(x) UW[(x) ^ 3]
#define UD(x) UD[(x) ^ 1]
#define Q(x) Q[x]
#else
#define B(x) B[x]
#define H(x) H[x]
#define W(x) W[x]
#define D(x) D[x]
#define UB(x) UB[x]
#define UH(x) UH[x]
#define UW(x) UW[x]
#define UD(x) UD[x]
#define Q(x) Q[x]
#endif /* HOST_BIG_ENDIAN */
#define DO_ADD(a, b) (a + b)
#define DO_SUB(a, b) (a - b)
#define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1))
#define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1))
#define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a))
#define DO_VABS(a) ((a < 0) ? (-a) : (a))
#define DO_MIN(a, b) (a < b ? a : b)
#define DO_MAX(a, b) (a > b ? a : b)
#define DO_MUL(a, b) (a * b)
#define DO_MADD(a, b, c) (a + b * c)
#define DO_MSUB(a, b, c) (a - b * c)
#define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
#define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
#define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
#define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
#define DO_SIGNCOV(a, b) (a == 0 ? 0 : a < 0 ? -b : b)
#define R_SHIFT(a, b) (a >> b)
#define DO_CLO_B(N) (clz32(~N & 0xff) - 24)
#define DO_CLO_H(N) (clz32(~N & 0xffff) - 16)
#define DO_CLO_W(N) (clz32(~N))
#define DO_CLO_D(N) (clz64(~N))
#define DO_CLZ_B(N) (clz32(N) - 24)
#define DO_CLZ_H(N) (clz32(N) - 16)
#define DO_CLZ_W(N) (clz32(N))
#define DO_CLZ_D(N) (clz64(N))
#define DO_BITCLR(a, bit) (a & ~(1ull << bit))
#define DO_BITSET(a, bit) (a | 1ull << bit)
#define DO_BITREV(a, bit) (a ^ (1ull << bit))
#define VSEQ(a, b) (a == b ? -1 : 0)
#define VSLE(a, b) (a <= b ? -1 : 0)
#define VSLT(a, b) (a < b ? -1 : 0)
#define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
#endif /* LOONGARCH_VEC_H */

3494
target/loongarch/vec_helper.c Normal file
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File diff suppressed because it is too large Load Diff