Block-TLB support and linux-user fixes for hppa target
All 32-bit hppa CPUs allow a fixed number of TLB entries to have a different page size than the default 4k. Those are called "Block-TLBs" and are created at startup by the operating system and managed by the firmware of hppa machines through the firmware PDC_BLOCK_TLB call. This patchset adds the necessary glue to SeaBIOS-hppa and qemu to allow up to 16 BTLB entries in the emulation. Two patches from Mikulas Patocka fix signal delivery issues in linux-user on hppa. -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZQnz0wAKCRD3ErUQojoP X6NDAP9F1Huhceot8peohGodRDOhnXWfDcjQZSDvadieKv/rJQEA60Z5QV5VlQgw SyUT4AcoiB7N4nvS+iDa+6dKfRH/YQM= =kqqt -----END PGP SIGNATURE----- Merge tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa into staging Block-TLB support and linux-user fixes for hppa target All 32-bit hppa CPUs allow a fixed number of TLB entries to have a different page size than the default 4k. Those are called "Block-TLBs" and are created at startup by the operating system and managed by the firmware of hppa machines through the firmware PDC_BLOCK_TLB call. This patchset adds the necessary glue to SeaBIOS-hppa and qemu to allow up to 16 BTLB entries in the emulation. Two patches from Mikulas Patocka fix signal delivery issues in linux-user on hppa. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZQnz0wAKCRD3ErUQojoP # X6NDAP9F1Huhceot8peohGodRDOhnXWfDcjQZSDvadieKv/rJQEA60Z5QV5VlQgw # SyUT4AcoiB7N4nvS+iDa+6dKfRH/YQM= # =kqqt # -----END PGP SIGNATURE----- # gpg: Signature made Tue 19 Sep 2023 15:17:39 EDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'hppa-btlb-pull-request' of https://github.com/hdeller/qemu-hppa: linux-user/hppa: lock both words of function descriptor linux-user/hppa: clear the PSW 'N' bit when delivering signals target/hppa: Wire up diag instruction to support BTLB target/hppa: Extract diagnose immediate value target/hppa: Add BTLB support to hppa TLB functions target/hppa: Report and clear BTLBs via fw_cfg at startup target/hppa: Allow up to 16 BTLB entries target/hppa: Update to SeaBIOS-hppa version 9 Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
commit
cb8a8b2ca9
@ -133,14 +133,10 @@ static FWCfgState *create_fw_cfg(MachineState *ms)
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fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPPA_TLB_ENTRIES);
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val = cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPPA_BTLB_ENTRIES);
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fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries",
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g_memdup(&val, sizeof(val)), sizeof(val));
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val = cpu_to_le64(HPA_POWER_BUTTON);
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fw_cfg_add_file(fw_cfg, "/etc/power-button-addr",
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g_memdup(&val, sizeof(val)), sizeof(val));
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@ -433,6 +429,10 @@ static void hppa_machine_reset(MachineState *ms, ShutdownCause reason)
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cs->exception_index = -1;
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cs->halted = 0;
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/* clear any existing TLB and BTLB entries */
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memset(cpu[i]->env.tlb, 0, sizeof(cpu[i]->env.tlb));
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cpu[i]->env.tlb_last = HPPA_BTLB_ENTRIES;
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}
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/* already initialized by machine_hppa_init()? */
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@ -149,16 +149,18 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
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target_ulong *fdesc, dest;
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haddr &= -4;
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if (!lock_user_struct(VERIFY_READ, fdesc, haddr, 1)) {
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fdesc = lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), 1);
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if (!fdesc) {
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goto give_sigsegv;
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}
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__get_user(dest, fdesc);
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__get_user(env->gr[19], fdesc + 1);
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unlock_user_struct(fdesc, haddr, 1);
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unlock_user(fdesc, haddr, 0);
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haddr = dest;
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}
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env->iaoq_f = haddr;
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env->iaoq_b = haddr + 4;
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env->psw_n = 0;
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return;
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give_sigsegv:
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Binary file not shown.
@ -1 +1 @@
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Subproject commit 673d2595d4f773cc266cbf8dbaf2f475a6adb949
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Subproject commit 763e3b73499db5fef94087bd310bfc8ccbcf7858
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@ -211,8 +211,14 @@ typedef struct CPUArchState {
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target_ureg shadow[7]; /* shadow registers */
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/* ??? The number of entries isn't specified by the architecture. */
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#ifdef TARGET_HPPA64
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#define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-bit machines */
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#else
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#define HPPA_BTLB_FIXED 16
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#endif
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#define HPPA_BTLB_VARIABLE 0
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#define HPPA_TLB_ENTRIES 256
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#define HPPA_BTLB_ENTRIES 0
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#define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE)
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/* ??? Implement a unified itlb/dtlb for the moment. */
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/* ??? We should use a more intelligent data structure. */
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@ -344,7 +350,8 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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void hppa_cpu_do_interrupt(CPUState *cpu);
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bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot);
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int type, hwaddr *pphys, int *pprot,
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hppa_tlb_entry **tlb_entry);
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extern const MemoryRegionOps hppa_io_eir_ops;
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extern const VMStateDescription vmstate_hppa_cpu;
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void hppa_cpu_alarm_timer(void *);
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@ -95,4 +95,5 @@ DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl)
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DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env)
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DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl)
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DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env)
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DEF_HELPER_1(diag_btlb, void, env)
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#endif
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@ -528,4 +528,4 @@ fdiv_d 001110 ..... ..... 011 ..... ... ..... @f0e_d_3
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xmpyu 001110 ..... ..... 010 .0111 .00 t:5 r1=%ra64 r2=%rb64
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# diag
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diag 000101 ----- ----- ---- ---- ---- ----
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diag 000101 i:26
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@ -154,7 +154,7 @@ void hppa_cpu_do_interrupt(CPUState *cs)
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vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr);
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t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
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0, &paddr, &prot);
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0, &paddr, &prot, NULL);
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if (t >= 0) {
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/* We can't re-load the instruction. */
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env->cr[CR_IIR] = 0;
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@ -41,16 +41,24 @@ static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr)
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return NULL;
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}
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static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
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static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent,
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bool force_flush_btlb)
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{
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CPUState *cs = env_cpu(env);
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unsigned i, n = 1 << (2 * ent->page_size);
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uint64_t addr = ent->va_b;
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if (!ent->entry_valid) {
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return;
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}
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trace_hppa_tlb_flush_ent(env, ent, ent->va_b, ent->va_e, ent->pa);
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for (i = 0; i < n; ++i, addr += TARGET_PAGE_SIZE) {
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tlb_flush_page_by_mmuidx(cs, addr, HPPA_MMU_FLUSH_MASK);
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tlb_flush_range_by_mmuidx(cs, ent->va_b,
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ent->va_e - ent->va_b + 1,
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HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS);
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/* never clear BTLBs, unless forced to do so. */
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if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) {
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return;
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}
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memset(ent, 0, sizeof(*ent));
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@ -60,23 +68,35 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tlb_entry *ent)
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static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env)
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{
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hppa_tlb_entry *ent;
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uint32_t i = env->tlb_last;
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uint32_t i;
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if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >= ARRAY_SIZE(env->tlb)) {
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i = HPPA_BTLB_ENTRIES;
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env->tlb_last = HPPA_BTLB_ENTRIES + 1;
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} else {
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i = env->tlb_last;
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env->tlb_last++;
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}
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env->tlb_last = (i == ARRAY_SIZE(env->tlb) - 1 ? 0 : i + 1);
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ent = &env->tlb[i];
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hppa_flush_tlb_ent(env, ent);
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hppa_flush_tlb_ent(env, ent, false);
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return ent;
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}
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int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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int type, hwaddr *pphys, int *pprot)
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int type, hwaddr *pphys, int *pprot,
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hppa_tlb_entry **tlb_entry)
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{
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hwaddr phys;
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int prot, r_prot, w_prot, x_prot, priv;
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hppa_tlb_entry *ent;
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int ret = -1;
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if (tlb_entry) {
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*tlb_entry = NULL;
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}
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/* Virtual translation disabled. Direct map virtual to physical. */
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if (mmu_idx == MMU_PHYS_IDX) {
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phys = addr;
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@ -93,8 +113,12 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
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goto egress;
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}
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if (tlb_entry) {
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*tlb_entry = ent;
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}
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/* We now know the physical address. */
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phys = ent->pa + (addr & ~TARGET_PAGE_MASK);
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phys = ent->pa + (addr - ent->va_b);
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/* Map TLB access_rights field to QEMU protection. */
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priv = MMU_IDX_TO_PRIV(mmu_idx);
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@ -193,7 +217,7 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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}
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excp = hppa_get_physical_address(&cpu->env, addr, MMU_KERNEL_IDX, 0,
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&phys, &prot);
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&phys, &prot, NULL);
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/* Since we're translating for debugging, the only error that is a
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hard error is no translation at all. Otherwise, while a real cpu
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@ -207,6 +231,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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hppa_tlb_entry *ent;
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int prot, excp, a_prot;
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hwaddr phys;
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@ -223,7 +248,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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}
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excp = hppa_get_physical_address(env, addr, mmu_idx,
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a_prot, &phys, &prot);
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a_prot, &phys, &prot, &ent);
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if (unlikely(excp >= 0)) {
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if (probe) {
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return false;
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@ -243,7 +268,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
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phys & TARGET_PAGE_MASK, size, type, mmu_idx);
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/* Success! Store the translation into the QEMU TLB. */
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tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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prot, mmu_idx, TARGET_PAGE_SIZE << (ent ? 2 * ent->page_size : 0));
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return true;
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}
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@ -254,11 +279,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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int i;
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/* Zap any old entries covering ADDR; notice empty entries on the way. */
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for (i = 0; i < ARRAY_SIZE(env->tlb); ++i) {
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for (i = HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) {
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hppa_tlb_entry *ent = &env->tlb[i];
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if (ent->va_b <= addr && addr <= ent->va_e) {
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if (ent->entry_valid) {
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hppa_flush_tlb_ent(env, ent);
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hppa_flush_tlb_ent(env, ent, false);
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}
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if (!empty) {
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empty = ent;
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@ -278,16 +303,8 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa);
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}
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/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
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void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target_ureg reg)
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{
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hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
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if (unlikely(ent == NULL)) {
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qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
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return;
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}
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ent->access_id = extract32(reg, 1, 18);
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ent->u = extract32(reg, 19, 1);
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ent->ar_pl2 = extract32(reg, 20, 2);
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@ -301,6 +318,19 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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ent->ar_pl1, ent->ar_type, ent->b, ent->d, ent->t);
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}
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/* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */
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void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg)
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{
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hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
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if (unlikely(ent == NULL)) {
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qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n");
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return;
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}
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set_access_bits(env, ent, reg);
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}
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/* Purge (Insn/Data) TLB. This is explicitly page-based, and is
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synchronous across all processors. */
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static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
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@ -310,7 +340,7 @@ static void ptlb_work(CPUState *cpu, run_on_cpu_data data)
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hppa_tlb_entry *ent = hppa_find_tlb(env, addr);
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if (ent && ent->entry_valid) {
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hppa_flush_tlb_ent(env, ent);
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hppa_flush_tlb_ent(env, ent, false);
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}
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}
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@ -334,7 +364,10 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong addr)
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void HELPER(ptlbe)(CPUHPPAState *env)
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{
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trace_hppa_tlb_ptlbe(env);
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memset(env->tlb, 0, sizeof(env->tlb));
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qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n");
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memset(&env->tlb[HPPA_BTLB_ENTRIES], 0,
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sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0]));
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env->tlb_last = HPPA_BTLB_ENTRIES;
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tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK);
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}
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@ -356,7 +389,7 @@ target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr)
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int prot, excp;
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excp = hppa_get_physical_address(env, addr, MMU_KERNEL_IDX, 0,
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&phys, &prot);
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&phys, &prot, NULL);
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if (excp >= 0) {
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if (env->psw & PSW_Q) {
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/* ??? Needs tweaking for hppa64. */
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@ -379,3 +412,95 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
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hppa_tlb_entry *ent = hppa_find_tlb(env, vaddr);
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return ent ? ent->ar_type : -1;
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}
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/*
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* diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to
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* allow operating systems to modify the Block TLB (BTLB) entries.
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* For implementation details see page 1-13 in
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* https://parisc.wiki.kernel.org/images-parisc/e/ef/Pdc11-v0.96-Ch1-procs.pdf
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*/
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void HELPER(diag_btlb)(CPUHPPAState *env)
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{
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unsigned int phys_page, len, slot;
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int mmu_idx = cpu_mmu_index(env, 0);
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uintptr_t ra = GETPC();
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hppa_tlb_entry *btlb;
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uint64_t virt_page;
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uint32_t *vaddr;
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#ifdef TARGET_HPPA64
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/* BTLBs are not supported on 64-bit CPUs */
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env->gr[28] = -1; /* nonexistent procedure */
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return;
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#endif
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env->gr[28] = 0; /* PDC_OK */
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switch (env->gr[25]) {
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case 0:
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/* return BTLB parameters */
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qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INFO\n");
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vaddr = probe_access(env, env->gr[24], 4 * sizeof(target_ulong),
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MMU_DATA_STORE, mmu_idx, ra);
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if (vaddr == NULL) {
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env->gr[28] = -10; /* invalid argument */
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} else {
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vaddr[0] = cpu_to_be32(1);
|
||||
vaddr[1] = cpu_to_be32(16 * 1024);
|
||||
vaddr[2] = cpu_to_be32(HPPA_BTLB_FIXED);
|
||||
vaddr[3] = cpu_to_be32(HPPA_BTLB_VARIABLE);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
/* insert BTLB entry */
|
||||
virt_page = env->gr[24]; /* upper 32 bits */
|
||||
virt_page <<= 32;
|
||||
virt_page |= env->gr[23]; /* lower 32 bits */
|
||||
phys_page = env->gr[22];
|
||||
len = env->gr[21];
|
||||
slot = env->gr[19];
|
||||
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_INSERT "
|
||||
"0x%08llx-0x%08llx: vpage 0x%llx for phys page 0x%04x len %d "
|
||||
"into slot %d\n",
|
||||
(long long) virt_page << TARGET_PAGE_BITS,
|
||||
(long long) (virt_page + len) << TARGET_PAGE_BITS,
|
||||
(long long) virt_page, phys_page, len, slot);
|
||||
if (slot < HPPA_BTLB_ENTRIES) {
|
||||
btlb = &env->tlb[slot];
|
||||
/* force flush of possibly existing BTLB entry */
|
||||
hppa_flush_tlb_ent(env, btlb, true);
|
||||
/* create new BTLB entry */
|
||||
btlb->va_b = virt_page << TARGET_PAGE_BITS;
|
||||
btlb->va_e = btlb->va_b + len * TARGET_PAGE_SIZE - 1;
|
||||
btlb->pa = phys_page << TARGET_PAGE_BITS;
|
||||
set_access_bits(env, btlb, env->gr[20]);
|
||||
btlb->t = 0;
|
||||
btlb->d = 1;
|
||||
} else {
|
||||
env->gr[28] = -10; /* invalid argument */
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
/* Purge BTLB entry */
|
||||
slot = env->gr[22];
|
||||
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\n",
|
||||
slot);
|
||||
if (slot < HPPA_BTLB_ENTRIES) {
|
||||
btlb = &env->tlb[slot];
|
||||
hppa_flush_tlb_ent(env, btlb, true);
|
||||
} else {
|
||||
env->gr[28] = -10; /* invalid argument */
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
/* Purge all BTLB entries */
|
||||
qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n");
|
||||
for (slot = 0; slot < HPPA_BTLB_ENTRIES; slot++) {
|
||||
btlb = &env->tlb[slot];
|
||||
hppa_flush_tlb_ent(env, btlb, true);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
env->gr[28] = -2; /* nonexistent option */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -179,7 +179,8 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr,
|
||||
return 0;
|
||||
}
|
||||
|
||||
excp = hppa_get_physical_address(env, addr, level, 0, &phys, &prot);
|
||||
excp = hppa_get_physical_address(env, addr, level, 0, &phys,
|
||||
&prot, NULL);
|
||||
if (excp >= 0) {
|
||||
if (env->psw & PSW_Q) {
|
||||
/* ??? Needs tweaking for hppa64. */
|
||||
|
||||
@ -4042,9 +4042,18 @@ static bool trans_fmpyfadd_d(DisasContext *ctx, arg_fmpyfadd_d *a)
|
||||
|
||||
static bool trans_diag(DisasContext *ctx, arg_diag *a)
|
||||
{
|
||||
qemu_log_mask(LOG_UNIMP, "DIAG opcode ignored\n");
|
||||
cond_free(&ctx->null_cond);
|
||||
return true;
|
||||
nullify_over(ctx);
|
||||
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
if (a->i == 0x100) {
|
||||
/* emulate PDC BTLB, called by SeaBIOS-hppa */
|
||||
gen_helper_diag_btlb(cpu_env);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
qemu_log_mask(LOG_UNIMP, "DIAG opcode 0x%04x ignored\n", a->i);
|
||||
}
|
||||
return nullify_end(ctx);
|
||||
}
|
||||
|
||||
static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user