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tcg/riscv: Enable native vector support for TCG host

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Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241007025700.47259-13-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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TANG Tiancheng 2024-10-07 10:57:00 +08:00 committed by Richard Henderson
parent d1843219a1
commit 4b7868f8c2
1 changed files with 3 additions and 3 deletions
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6
tcg/riscv/tcg-target.h
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@ -143,9 +143,9 @@ typedef enum {
#define TCG_TARGET_HAS_tst 0 #define TCG_TARGET_HAS_tst 0
/* vector instructions */ /* vector instructions */
#define TCG_TARGET_HAS_v64 0 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_v128 0 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_v256 0 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X)
#define TCG_TARGET_HAS_andc_vec 0 #define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_nand_vec 0 #define TCG_TARGET_HAS_nand_vec 0